Methods of fabricating semiconductor packages including reinforcement top die
A method of fabricating semiconductor packages may include forming stack structures on a base die wafer, disposing a top die wafer on the stack structures, and forming a molding layer filling a space between the base die wafer and the top die wafer.
1. A method of fabricating semiconductor packages, the method comprising:
forming stack structures on a base die wafer;
disposing a top die wafer on the stack structures; and
forming a molding layer filling a space between the base die wafer and the top die wafer,
wherein the stack structures are comprised of core dies,
wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions; and
wherein the stack structures overlap with the base die regions, respectively, in a plan view,
further comprising removing the peripheral region of the base die wafer, a portion of the molding layer overlapping with the peripheral region, and a portion of the top die wafer overlapping with the peripheral region.
2. The method of claim 1 , wherein the top die wafer has a thickness which is greater than a thickness of the base die wafer.
3. The method of claim 1 , wherein the top die wafer has a thickness which is greater than a thickness of each of the core dies.
4. The method of claim 1 , wherein the top die wafer is a dummy silicon wafer.
5. The method of claim 1 , wherein each of the base die regions further includes first through vias that substantially penetrate the base die region.
6. The method of claim 5 ,
wherein each of the core dies further includes second through vias that substantially penetrate the core die; and
wherein the second through vias are electrically connected to the first through vias.
7. A method of fabricating semiconductor packages, the method comprising:
forming stack structures on a base die wafer;
disposing a top die wafer on the stack structures; and
forming a molding layer filling a space between the base die wafer and the top die wafer,
wherein the stack structures are comprised of core dies,
wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions;
wherein the stack structures overlap with the base die regions, respectively, in a plan view,
wherein the core dies are memory semiconductor dies; and
wherein each of the base die regions is a logic semiconductor die in which a controller device for controlling the memory semiconductor dies is integrated.
8. A method of fabricating semiconductor packages, the method comprising:
forming stack structures on a base die wafer;
disposing a top die wafer having a trench, which is opened toward the base die wafer, on the stack structures; and
forming a molding layer filling a space between the base die wafer and the top die wafer,
wherein the base die wafer includes base die regions in which integrated circuits are realized and a peripheral region between the base die regions;
wherein the stack structures overlap with the base die regions, respectively, in a plan view; and
wherein the trench of the top die wafer is disposed to overlap with the peripheral region of the base die wafer.
9. The method of claim 8 , wherein the top die wafer has a thickness which is greater than a thickness of the base die wafer.
10. The method of claim 8 , wherein the stack structures are comprised of core dies.
11. The method of claim 10 , wherein the top die wafer has a thickness which is greater than a thickness of each of the core dies.
12. The method of claim 8 , wherein the molding layer extends to have a filling portion that fills the trench of the top die wafer overlapping with the peripheral region of the base die wafer, and
the method further comprises reducing a thickness of the top die wafer to expose a top surface of the filling portion of the molding layer after forming the molding layer.
13. The method of claim 12 , wherein the top die wafer is divided into top dies which are isolated from each other by the filling portion if the top surface of the filling portion is exposed.
14. The method of claim 12 , further comprising removing the peripheral region of the base die wafer, a portion of the molding layer overlapping with the peripheral region, and a portion of the filling portion of the molding layer overlapping with the peripheral region.
15. The method of claim 8 , wherein the trench of the top die wafer has a width which is greater than a width of the peripheral region of the base die wafer.