Multi-processor core device with MBIST
In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.
1. An embedded device comprising:
a plurality of processor cores, each processor core comprising:
a static random access memory (SRAM);
a memory built-in self-test (MBIST) controller associated with the SRAM;
an MBIST access port coupled with the MBIST controller; and
an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer;
and
a JTAG interface coupled with the MBIST access ports of each processor core via the first multiplexer of each processor core,
wherein each BIST controller is individually configurable through the associated FSM and user software to perform a memory self test after a reset of the embedded device.
2. The embedded device according to claim 1 , wherein the plurality of processor cores consists of a master core and a slave core.
3. The embedded device according to claim 1 , wherein the plurality of processor cores comprises a single master core and at least one slave core.
4. The embedded device according to claim 3 , wherein the slave core comprises a slave program static random access memory (PRAM) and an associated MBIST Controller coupled with the MBIST access port.
5. The embedded device according to claim 4 , wherein a data output of the MBIST access port is coupled with a data input of the BIST controller associated with the SRAM, wherein a data output of the BIST controller associated with the SRAM is coupled with a data input of the BIST controller associated with the PRAM and wherein a data output of the BIST controller associated with the PRAM is coupled with a data input of the BIST access port.
6. The embedded device according to claim 1 , wherein a reset is initiated by an external reset, a software reset instruction or a watchdog reset.
7. The embedded device according to claim 1 , wherein each processor core comprises a clock source providing a clock to an associated FSM.
8. The embedded device according to claim 7 , wherein different clock sources are selected for MBIST FSM of the plurality of processor cores.
9. The embedded device according to claim 3 , wherein each FSM comprises a control register coupled with a respective processing core.
10. The embedded device according to claim 3 , wherein a reset sequence of a processing core is extended until a memory test has finished.
11. The embedded device according to claim 10 , wherein a signal supplied from the FSM is used to control extension of the reset sequence.
12. The embedded device according to claim 3 , further comprising configuration fuses in the master core for configuring the master MBIST functionality and each slave MBIST functionality.
13. A method for operating an embedded device comprising a plurality of processor cores, each processor core comprising a static random access memory (SRAM), a memory built-in self test (MBIST) controller associated with the SRAM, an MBIST access port coupled with MBIST controller, and an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, the embedded device further comprising a JTAG interface coupled with the MBIST access port of each processor core via the first multiplexer of each processor core, the method comprising:
configuring an MBIST functionality for each processor core separately wherein MBIST is controlled by an FSM of each processor core through the first multiplexer;
performing a reset of at least one of the processor cores; and
during a reset sequence, performing the MIST for the reset processor core.
14. The method according to claim 13 , further comprising providing the plurality of processor cores by a single master core and at least one slave core.
15. The method according to claim 14 , further comprising providing the slave core with a slave program static random access memory (PRAM) and an associated MBIST Controller coupled with the MBIST access port.
16. The method according to claim 14 , further comprising configuring each BIST controller individually to perform a memory self test by configuring a fuse in the master core.
17. The method according to claim 13 , wherein a reset is initiated by an external reset, a software reset instruction or a watchdog reset.
18. The method according to claim 13 , further comprising providing a clock to an FSM through a clock source within each processor core.
19. The method according to claim 18 , further comprising selecting different clock sources for an MBIST FSM of the plurality of processor cores.
20. The method according to claim 14 , wherein each FSM comprises a control register coupled with a respective processing core.
21. The method according to claim 14 , wherein a reset sequence of a processing core is extended until a memory test has finished.
22. The method according to claim 21 , wherein a signal fed to the FSM is used to control extension of the reset sequence.
23. The method according to claim 13 , further comprising initiating the MBIST during operation of the embedded device by stalling access to an SRAM by an associated processor core and performing the MBIST on the SRAM.
24. A method for operating an embedded device comprising a plurality of processor cores, each processor core comprising a static random access memory (SRAM), a memory built-in self test (MBIST) controller associated with the SRAM, an MBIST access port coupled with MBIST controller, and an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, the embedded device further comprising a JTAG interface coupled with the MBIST access port of each processor core via the first multiplexer of each processor core, the method comprising:
operating the embedded device;
configuring an MBIST functionality for an SRAM of at least one core wherein MBIST is controlled by an FSM of the at least one core through the multiplexer;
stalling processor access to the SRAM; and
performing the MBIST for SRAM.