IP Library › Granted Patent US 10,217,711
Granted Patent B2
US 10,217,711 · App. 15/789,070 · Granted Feb 26, 2019

Semiconductor package and manufacturing method thereof

Inventors: Sung Jae Yoon (Suwon-si, KR); Seong Jong Cheon (Suwon-si, KR)
Assignee: Samsung Electro-Mechanics Co., Ltd.
H01L23/552H01L21/561H01L23/3121H01L23/3135H01L23/4334H01L23/49838H01L25/0655H01L23/49805H01L23/49822
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Quick Facts
Patent No.
US 10,217,711
App. No.
15/789,070
Granted
Feb 26, 2019
Kind
B2
Abstract

A semiconductor package includes a ground electrode formed on an upper surface of a substrate, a first electronic component disposed on the upper surface of the substrate, a sealing member sealing the electronic component, and a shielding member surrounding the first electronic component and disposed in the sealing member.

Claims (34)

1. A semiconductor package, comprising:

a substrate;

a ground electrode disposed on an upper surface of the substrate;

at least one electronic component disposed on the upper surface of the substrate;

an internal sealing member sealing the electronic component; and

a shielding member surrounding the electronic component and disposed in an external sealing member,

wherein the shielding member separates the internal sealing member from the external sealing member.

2. The semiconductor package of claim 1 , wherein the entire internal sealing member is blocked from contact with the external sealing member by the shielding member.

3. The semiconductor package of claim 2 , wherein a portion of the ground electrode is exposed externally of the internal sealing member and the ground electrode is connected to the shielding member.

4. The semiconductor package of claim 1 , wherein the shielding member is in surface contact with the electronic component and the ground electrode.

5. The semiconductor package of claim 4 , wherein the shielding member is in surface contact with the substrate.

6. The semiconductor package of claim 1 , further comprising at least one electronic component disposed outside the shielding member.

7. The semiconductor package of claim 1 ,

wherein the electronic component is mounted on the substrate using a flip chip bonding method, and

wherein a portion of the shielding member is disposed on an inactive surface of the electronic component.

8. A method of manufacturing the semiconductor package of claim 1 , the method comprising:

disposing an electronic component on a substrate, the substrate comprising a ground electrode;

partially embedding the electronic component with an internal sealing member;

surrounding the electronic component and the internal sealing member with a shielding member; and

embedding the shielding member with an external sealing member.

9. The method of claim 8 , wherein the shielding member is disposed using a sputtering method or a vapor deposition method.

10. The method of claim 8 , wherein the forming of the internal sealing member comprises:

completely embedding the electronic component and the ground electrode with a sealing member; and

partially removing the sealing member to expose the electronic component and the ground electrode.

11. The method of claim 10 , wherein the removing of the sealing member comprises exposing an inactive surface of the electronic component by polishing the sealing member.

12. The method of claim 10 , wherein the removing of the sealing member comprises exposing the ground electrode using a laser drilling method or an etching method.

13. The method of claim 8 , wherein the shielding member is disposed along the internal sealing member, surfaces of the electronic component, and the ground electrode exposed externally of the internal sealing member.

14. The method of claim 8 , wherein the mounting of the electronic component comprises bonding the electronic component having a form of a bare die to the substrate using a flip chip bonding method.

15. The method of claim 8 , wherein the semiconductor package comprises a plurality of semiconductor packages disposed adjacent to one another and sharing a same substrate.

16. The method of claim 15 , further comprising cutting the shared same substrate to form individual semiconductor packages.

17. The semiconductor package of claim 1 , wherein the shielding member seals the internal sealing member inside the shielding member.

18. The semiconductor package of claim 1 , wherein the shielding member comprises a thin film.

19. The semiconductor package of claim 18 , wherein the shielding member comprises a metal thin film.

20. The semiconductor package of claim 1 , wherein the shielding member comprises a planar flange in direct contact with the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2017
From: YOON, SUNG JAE; CHEON, SEONG JONG
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 043911/0329 →
Priority Claims (1)
KR 10-2017-0036739 · Mar 23, 2017 · national
Continuity (1)
Related Publication 20180277490A1 · Sep 27, 2018
Cited By (2)
US 12,356,538 US 12,402,289