IP Library › Granted Patent US 10,163,635
Granted Patent B1
US 10,163,635 · App. 15/797,794 · Granted Dec 25, 2018

Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method

Inventors: Yi Qi (Niskayuna, NY); Hui Zang (Guilderland, NY); Hsien-Ching Lo (Clifton Park, NY); Jerome Ciavatti (Mechanicville, NY); Judson Robert Holt (Ballston Lake, NY)
Assignee: GLOBALFOUNDRIES INC.
H01L21/0337H01L21/02532H01L21/02592H01L21/30625H01L21/31105H01L29/0657H01L28/40H01L29/785H01L29/8613
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Quick Facts
Patent No.
US 10,163,635
App. No.
15/797,794
Granted
Dec 25, 2018
Kind
B1
Abstract

A method for preventing epitaxial merge between adjacent devices of a semiconductor is provided. Embodiments include forming a protection layer over a spacer formed over a first and second plurality of fins deposited within a substrate; pinching off a portion of the protection layer formed within a space between each of the plurality of fins; forming a planarization layer over the protection layer and the spacer; and etching a portion of the spacer to form inner sidewalls between each of the plurality of fins, outer sidewalls of a height greater than the height of the inner sidewalls for preventing the growth of the epitaxial layer beyond the outer sidewalls, or a combination thereof.

Claims (40)

1. A method comprising:

forming a protection layer over a spacer formed over a first and second plurality of fins deposited within a substrate;

pinching off a portion of the protection layer formed within a space between each of the plurality of fins;

forming a planarization layer over the protection layer and the spacer; and

etching a portion of the spacer to form inner sidewalls between each of the plurality of fins, outer sidewalls of a height greater than the height of the inner sidewalls for preventing the growth of the epitaxial layer beyond the outer sidewalls, or a combination thereof.

2. The method of claim 1 , further comprising:

growing the epitaxial layer within the bounds of the inner sidewalls, the outer sidewalls, or a combination thereof to form asymmetric diamond shaped crystals,

wherein the growth includes a merging of the crystals.

3. The method of claim 1 , wherein the forming of the planarization layer further comprises:

depositing an organic material, an amorphous silicon material, or a combination thereof as the planarization layer,

wherein the deposit is based on an etch selectivity requirement being achieved through use of the organic material in comparison with a lower dielectric value of the spacer.

4. The method of claim 3 , further comprising:

polishing the amorphous silicon material to a high modularity,

wherein the polishing is performed chemically, mechanically or a combination thereof.

5. The method of claim 1 , further comprising:

recessing the planarization layer to a height below each of the plurality of fins,

wherein the planarization layer remains between the first and second plurality of fins after the recession.

6. The method of claim 1 , further comprising:

etching the protection layer,

wherein the protection layer is formed from one or more of an amorphous hydrogenated carbon (a-C), amorphous silicon (a-Si), aluminum oxide (Al2O3), a polymer or a combination thereof.

7. The method of claim 6 , further comprising:

removing the pinched off portion of the protection layer and the portion of the protection layer formed between the first and second plurality of fins,

wherein the pinched off portion is a chamfer for supporting the removal.

8. The method of claim 6 , wherein further comprising:

removing the pinched off portion of the protection layer and reducing the portion of the protection layer formed between the first and second plurality of fins,

wherein the reduction is to the height of the reduced portion of the protection layer and the reduced portion of the protection layer is surrounded by the planarization layer.

9. The method of claim 8 , wherein the height of the reduced portion of the protection layer is greater than the height of the portion of the spacer formed between the first and second plurality of fins and the space between the first and second plurality of fins is a distance between a first and second device of a semiconductor.

10. The method of claim 9 , wherein the etching of the portion of the spacer formed between the first and second plurality of fins further comprises:

recessing the planarization layer; and

removing the reduced portion of the protection layer.

11. A method comprising:

forming fins in substrate for a device;

forming an asymmetric sidewall spacer placed along the sides of the device; and

forming an epitaxial layer within the device,

wherein a height of the asymmetrical sidewall spacer is greater than a height of internal sidewall spacers within the device.

12. The method of claim 11 , further comprising:

forming a internal sidewall spacers along the sides of each of the fins within the device,

wherein a lateral growth of the epitaxial layer is confined by the asymmetric sidewall spacer and the internal growth of the epitaxial layer within the device expands around the internal sidewall spacers, the plurality of fins, or a combination thereof.

13. The method of claim 11 , further comprising:

growing the epitaxial layer to form asymmetric diamond shaped crystals, wherein the crystals merge within the device.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2017
From: QI, YI; ZANG, HUI; LO, HSIEN-CHING; CIAVATTI, JEROME; HOLT, JUDSON ROBERT
To: GLOBALFOUNDRIES INC.
Reel/Frame 044109/0604 →
Cited By (2)
US 12,191,206 US 12,356,647