Microstructure enhanced absorption photosensitive devices
Microstructure enhanced photodiodes and avalanche photodiodes are monolithically integrated with CMOS/BiCMOS circuitry such as transimpedance amplifiers. Microstructures, such as holes, can improve quantum efficiency in silicon and III-V materials and can also reduce avalanche voltages for avalanche photodiodes. Applications include optical communications within and between datacenters, telecommunications, LIDAR, and free space data communication.
1. A single-chip device comprising an integrated combination of a microstructure-enhanced photodetector (MSPD) configured for reverse-bias operation and an active electronic circuit, both formed on or in a single substrate and configured to receive an optical input that in cross-section is substantially continuous, convert the optical input to an electrical output, and process the electrical output into a processed output, wherein:
the MSPD on or in said single substrate comprises an intermediate layer, a first layer at one side of the intermediate layer, and a second layer at an opposite side of the intermediate layer, wherein:
each of the layers comprises Silicon, Germanium, or an alloy thereof;
at least one of said layers, or an overlying covering layer that may be present, has holes intentionally formed therein, extending in directions transverse to the layers;
each of the first and second layers comprises a doped material;
the intermediate layer comprises a material that is less doped than at least one of the first and second layers or is undoped, wherein the degree of doping is the same or different for different positions in the intermediate layer;
an input portion configured to concurrently receive at a plurality of said holes said optical input that has said substantially continuous cross-section; and
an output portion configured to provide said electrical output from the MSPD;
the MSPD includes reverse-bias electrodes coupled therewith to establish an electrical field therein when energized to thereby sweep in a selected direction electrical charges generated in the MSPD by said optical input;
said reverse-bias electrodes being free of a pattern of openings that matches said holes; and
the active electronic circuit on or in said single substrate is configured to process the electrical output from the MSPD by applying thereto:
amplification to form said processed output from the single-chip device;
processing other than or in addition to amplification to form said processed output from the single-chip device; and
routing to one or more selected destinations; and
a communication channel on or in said single-chip device, configured to deliver the electrical output from the MSPD to the active electronic circuit.
2. The single-chip device of claim 1 , in which said active electronic circuit at least partly extends beyond said substrate.
3. The single-chip device of claim 1 , in which said active electronic circuit is at least partly inside said substrate.
4. The single-chip device of claim 1 , in which said overlying layer is present as a superstrate at one side of said first, intermediate, and second layers, and contains said holes.
5. The single-chip device of claim 1 , in which said MSPD comprises a III-V materials family photodiode.
6. The single-chip device of claim 1 , further including an air-filled volume between the substrate and the MSPD.
7. The single-chip device of claim 1 , further including a layer of a dielectric material that covers the holes and is in the propagation path of said optical input.
8. The single-chip device of claim 1 , further including an avalanche region at one side of the MSPD, forming therewith an avalanche microstructured photodiode (MSAPD).
9. The single-chip device of claim 1 , in which said holes are present in said intermediate layer.
10. The single-chip device of claim 1 , in which said holes are present in said intermediate layer as well as in at least one of the first and second layers.
11. The single-chip device of claim 1 , in which said holes are present in each of the first, second, and intermediate layer.
12. The single-chip device of claim 1 , in which each of said first and second layers and said intermediate layer has a thickness and at least some of said holes extend through the entire thickness of said intermediate layer and of one of said first layer and second layer and through at least a part of the thickness of the other one of said first and second layers.
13. The single-chip device of claim 1 , in which at least some of said holes are shaped as inverted pyramids.
14. The single-chip device of claim 1 , in which at least some of said holes have triangular sections in planes transverse to said layers.
15. The single-chip device of claim 1 , in which at least some of said holes have triangular sections in planes transverse to said layers, with vertices within the intermediate layer.
16. The single-chip device of claim 1 , in which at least some of said holes have sidewalls that slope in planes transverse to said layers.
17. The single-chip device of claim 1 , in which at least some of said holes have sidewalls with plural different slopes along the inside walls of the holes.
18. The single-chip device of claim 1 , in which at least some of said holes differ from each other in at least one of (i) distance by which the holes extend in said directions, (ii) shape of the holes, and (iii) spacing of the holes from each other.
19. The single-chip device of claim 1 , in which the holes are in the intermediate layer and wherein one of said first and second layers conformally covers inside walls of the holes as well as spaces between the holes.
20. The single-chip device of claim 1 , in which the holes are at least partly filled with a dielectric material.
21. The single-chip device of claim 1 , in which the holes are entirely filled with a dielectric material.
22. The single-chip device of claim 1 , in which said optical input enters the MSPD through one or both of said first and second layers, and each of the first and second layers through which the optical input enters is no more than 500 nanometers thick.
23. The single-chip device of claim 1 , in which at least one of the first layer, the second layer, and the intermediate layer comprises a material represented by Ge x Si 1-x , where x is greater than zero.
24. The single-chip device of claim 1 , in which said MSPD further comprises ohmic contacts configured for reverse-biasing the MSPD.
25. The single-chip device of claim 1 , in which the MSPD further includes ohmic contacts to said first and second layers, at least one of said ohmic contact being through a via in said substrate.
26. The single-chip device of claim 1 , further comprising a light guide to said MSPD for directing said optical input thereto, and electrical contacts from the active electronic circuit configured to carry said processed output out of the single-chip device.
27. The single-chip device of claim 1 , further comprising a light guide to said MSPD configured to bend the optical input from an initial propagation direction to a propagation direction transverse to said layers, and electrical contacts from the active electronic circuit configured to carry said processed output out of the single-chip device.
28. The single-chip device of claim 1 , further comprising one or more additional MSPD on or in the same substrate, and respective different optical bandpass filters coupled with at least two of the MSPDs on or in said single substrate, whereby at least two of said MSPDs are configured to respond to different wavelength ranges that are within said optical input.
29. The single-chip device of claim 1 , further comprising one or more additional MSPDs on or in said single substrate, one or more additional active electronic circuits on or in the said single substrate, and one or more additional communication channels configured to supply electrical outputs from the MSPDs to the one or more of the active electronic circuits.
30. The single-chip device of claim 1 , further comprising one or more additional active electronic circuits that are formed on or in the said single substrate.
31. The single-chip device of claim 1 , further comprising one or more additional active electronic circuits that are formed on or in the said single substrate and comprise one or more transimpedance amplifiers (TIAs) and one or more application specific integrated circuits (ASICs).
32. The single-chip device of claim 1 , further comprising one or more additional active electronic circuits that are formed on or in the said single substrate and comprise one or more of CMOS, BiCMOS, and bipolar active devices.
33. The single-chip device of claim 1 , further comprising one or more additional MSPDs in an array on or in said single substrate and one or more additional active electronic circuits also on or in said single substrate, said MSPDs and active electronic circuits being configured into an optical communication structure or a light distance and ranging (LIDAR) structure.
34. The single-chip device of claim 1 , further comprising a laser emitter formed on or in said single substrate.
35. The single-chip device of claim 1 , further including a layer of selected material that is over a side of one of the first and second layers facing away from the intermediate layer and is configured to reduce sheet resistance.
36. The single-chip device of claim 1 , further including a layer of selected material that is over a side of one of the first and second layers facing away from the intermediate layer and is configured to reflect light that has passed through the intermediate layer back toward the intermediate layer.
37. The single-chip device of claim 1 , further including a deliberately textured surface at a side of one of said first and second layers facing away from the intermediate layer.
38. The single-chip device of claim 1 , further including a layer of micro-nano structures formed at of one of said first and second facing, at a surface thereof facing away from the intermediate layer.
39. The single-chip device of claim 1 , further including one or more distributed Bragg reflectors formed at one of said first and second layers, at a surface thereof away from the intermediate layer.
40. The single-chip device of claim 1 , further including an isolation trench between the MSPD and the active electronic circuit.