IP Library Granted Patent US 10,483,187
Granted Patent B2
US 10,483,187 · App. 15/800,349 · Granted Nov 19, 2019

Heat spreading device and method

Inventors: Chen-Hua Yu (Hsinchu, TW); Wensen Hung (Zhubei, TW); Ming-Fa Chen (Taichung, TW); Tsung-Yu Chen (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/3738H01L21/4871H01L23/367H01L25/18H01L25/50H01L23/3736H01L23/42H01L2224/06155H01L2224/06519H01L2224/17155H01L2224/17519H01L2924/15311H01L2924/16152
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Quick Facts
Patent No.
US 10,483,187
App. No.
15/800,349
Granted
Nov 19, 2019
Kind
B2
Abstract

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Claims (70)

1. A method comprising:

placing a die stack on a front side of a device wafer;

forming conductive connectors on a back side of the device wafer;

singulating the device wafer to form an integrated circuit die, the die stack disposed on the integrated circuit die;

placing the integrated circuit die on a carrier substrate;

bonding a front side of a dummy wafer to the integrated circuit die, the die stack disposed in a recess in the front side of the dummy wafer;

debonding the integrated circuit die from the carrier substrate; and

singulating the dummy wafer to form a dummy semiconductor feature, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die.

2. The method of claim 1 further comprising:

before the singulating the dummy wafer, thinning a back side of the dummy wafer until the recess is exposed, thereby forming an opening extending through the dummy wafer; and

forming an adhesive in the opening, top surfaces of the adhesive, the dummy wafer, and the die stack being level.

3. The method of claim 1 further comprising:

before the bonding the front side of the dummy wafer to the integrated circuit die, forming an adhesive on the die stack; and

placing the front side of the dummy wafer on the integrated circuit die, the adhesive filling the recess.

4. The method of claim 1 further comprising:

bonding the integrated circuit die to a package substrate with the conductive connectors;

forming an underfill between the package substrate and the integrated circuit die, the underfill surrounding the conductive connectors and the integrated circuit die; and

attaching a heat spreader to the package substrate, the heat spreader adhered to the dummy semiconductor feature.

5. A method comprising:

placing a die stack on a front side of a device wafer;

bonding a front side of a dummy wafer to the front side of the device wafer, the die stack disposed in a recess in the front side of the dummy wafer;

thinning a back side of the dummy wafer until the recess is exposed, thereby forming an opening extending through the dummy wafer;

forming a first adhesive in the opening, top surfaces of the first adhesive, the dummy wafer, and the die stack being level;

forming conductive connectors on a back side of the device wafer; and

singulating the device wafer and the dummy wafer simultaneously, the device wafer singulated to form an integrated circuit die, the die stack disposed on the integrated circuit die, the dummy wafer singulated to form a dummy semiconductor feature, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die.

6. The method of claim 5 further comprising:

forming vias extending from the front side of the dummy wafer into the dummy wafer.

7. The method of claim 5 further comprising:

bonding the integrated circuit die to a package substrate with the conductive connectors;

forming an underfill between the package substrate and the integrated circuit die, the underfill surrounding the conductive connectors;

dispensing a thermal interface material on the integrated circuit die and the dummy semiconductor feature; and

attaching a heat spreader to the package substrate and the thermal interface material, the thermal interface material thermally coupling the heat spreader to the dummy semiconductor feature and the integrated circuit die.

8. The method of claim 7 further comprising:

before the singulating the device wafer and the dummy wafer, forming dummy metallization on the dummy wafer, wherein after attaching the heat spreader to the package substrate, the dummy metallization thermally couples the thermal interface material to the dummy semiconductor feature and the integrated circuit die.

9. The method of claim 7 further comprising:

before attaching the heat spreader to the package substrate, dispensing a second adhesive on the dummy semiconductor feature and the integrated circuit die; and

forming dummy conductive features on the second adhesive, the thermal interface material being disposed on the second adhesive and surrounding the dummy conductive features.

10. The method of claim 5 further comprising:

bonding the integrated circuit die to a package substrate with the conductive connectors;

forming an underfill between the package substrate and the integrated circuit die, the underfill surrounding the conductive connectors; and

attaching a support ring to the package substrate, the support ring surrounding the integrated circuit die and the underfill.

11. A method comprising:

placing a die stack on a front side of an integrated circuit die;

forming a plurality of conductive connectors on a back side of the integrated circuit die;

bonding a dummy wafer to the front side of the integrated circuit die, the dummy wafer having a first portion covering the die stack after the bonding;

thinning the dummy wafer to remove the first portion of the dummy wafer, the die stack being exposed after the thinning;

forming a first adhesive between the die stack and the dummy wafer; and

singulating the dummy wafer to form a dummy semiconductor feature on the front side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature being electrically isolated from the die stack and the integrated circuit die.

12. The method of claim 11 further comprising:

forming the integrated circuit die in a device wafer; and

before bonding the dummy wafer to the front side of the integrated circuit die, singulating the integrated circuit die from the device wafer,

wherein the dummy wafer is bonded to the singulated integrated circuit die.

13. The method of claim 11 further comprising:

forming the integrated circuit die in a device wafer,

wherein the dummy wafer is bonded to the device wafer, and

wherein singulating the dummy wafer comprises simultaneously singulating the device wafer and the dummy wafer.

14. The method of claim 13 further comprising:

before singulating the device wafer and the dummy wafer, plating dummy metallization on the dummy wafer and the integrated circuit die.

15. The method of claim 11 , wherein bonding the dummy wafer to the front side of the integrated circuit die comprises forming fusion bonds between the dummy wafer and the integrated circuit die.

16. The method of claim 11 , wherein bonding the dummy wafer to the front side of the integrated circuit die comprises forming hybrid bonds between the dummy wafer and the integrated circuit die.

17. The method of claim 11 , wherein bonding the dummy wafer to the front side of the integrated circuit die comprises forming solder bonds between the dummy wafer and the integrated circuit die.

18. The method of claim 11 , wherein forming the first adhesive between the die stack and the dummy wafer comprises:

before the singulating the dummy wafer, thinning a back side of the dummy wafer until the die stack is exposed, thereby forming an opening extending through the dummy wafer; and

dispensing the first adhesive in the opening; and

planarizing the first adhesive and the dummy wafer such that top surfaces of the first adhesive, the dummy wafer, and the die stack are level.

19. The method of claim 11 , wherein forming the first adhesive between the die stack and the dummy wafer comprises:

before bonding the dummy wafer to the front side of the integrated circuit die, dispensing the first adhesive on the die stack; and

placing the dummy wafer on the first adhesive.

20. The method of claim 11 further comprising:

forming vias extending at least partially into the dummy wafer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2017
From: YU, CHEN-HUA; HUNG, WENSEN; CHEN, MING-FA; CHEN, TSUNG-YU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 044346/0996 →
Continuity (2)
Provisional Application 62527770 · Jun 30, 2017
Related Publication 20190006263A1 · Jan 3, 2019
Cited By (2)
US 12,482,721 US 12,660,649