Semiconductor package including heat dissipation structure
The present disclosure provides semiconductor packages including a heat dissipation structure. In some embodiments, the semiconductor package includes a package substrate, a stacked chip disposed on the package substrate and including a lower chip and an upper chip, a memory chip disposed on the package substrate adjacent to the stacked chip, and an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate. An upper surface of the upper chip is exposed from the encapsulant. A dummy silicon chip is in contact with the upper chip on the lower chip.
1 . A semiconductor package, comprising:
a package substrate;
a stacked chip disposed on the package substrate and comprising a lower chip and an upper chip;
a memory chip disposed on the package substrate adjacent to the stacked chip; and
an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate,
wherein an upper surface of the upper chip is exposed from the encapsulant, and
wherein a dummy silicon chip is in contact with the upper chip on the lower chip.
2 . The semiconductor package of claim 1 , wherein:
an upper surface of the dummy silicon chip is substantially coplanar with the upper surface of the upper chip, and
the upper surface of the dummy silicon chip is exposed from the encapsulant.
3 . The semiconductor package of claim 2 , wherein:
side surfaces of the dummy silicon chip are substantially coplanar with side surfaces of the encapsulant and the package substrate, and
the side surfaces of the dummy silicon chip are exposed from the encapsulant.
4 . The semiconductor package of claim 2 , wherein:
the dummy silicon chip comprises an upper portion and a lower portion,
a first thickness of the upper portion of the dummy silicon chip is smaller than a second thickness of the lower portion of the dummy silicon chip, and
side surfaces of the upper portion of the dummy silicon chip are exposed from the encapsulant.
5 . The semiconductor package of claim 4 , wherein the encapsulant is disposed on side surfaces of the lower chip and side surfaces of the lower portion of the dummy silicon chip.
6 . The semiconductor package of claim 1 , wherein:
the dummy silicon chip comprises a metal path, and
an end of the metal path is exposed to the outside of the dummy silicon chip.
7 . The semiconductor package of claim 6 , further comprising a heat sink coupled to the metal path.
8 . The semiconductor package of claim 1 , wherein the dummy silicon chip is bonded to the lower chip by using a thermally conductive adhesive layer.
9 . The semiconductor package of claim 1 , wherein the lower chip is bonded to the upper chip by using a hybrid bonding that is a combination of a pad-to-pad bonding and an insulator-to-insulator bonding.
10 . The semiconductor package of claim 1 , wherein the memory chip comprises a dynamic random access memory (DRAM) chip.
11 . The semiconductor package of claim 1 , wherein the memory chip has a high bandwidth memory (HBM) package structure comprising a plurality of dynamic random access memory (DRAM) chips.
12 . The semiconductor package of claim 1 , wherein the package substrate comprises a redistribution layer (RDL) substrate.
13 . A semiconductor package, comprising:
a redistribution substrate;
a stacked chip disposed on the redistribution substrate and comprising a lower chip and an upper chip;
a memory chip disposed on the redistribution substrate adjacent to the stacked chip;
a dummy silicon chip adjacent to the upper chip disposed on the lower chip; and
an encapsulant encapsulating the stacked chip, the memory chip, and the dummy silicon chip on the redistribution substrate,
wherein an upper surface of the upper chip and an upper surface of the dummy silicon chip are exposed from the encapsulant.
14 . The semiconductor package of claim 13 , wherein:
side surfaces of the dummy silicon chip are substantially coplanar with side surfaces of the redistribution substrate, and
the side surfaces of the dummy silicon chip are exposed from the encapsulant.
15 . The semiconductor package of claim 13 , wherein:
the dummy silicon chip comprises an upper portion and a lower portion,
a first thickness of the upper portion of the dummy silicon chip is smaller than a second thickness of the lower portion of the dummy silicon chip,
side surfaces of the upper portion of the dummy silicon chip are exposed from the encapsulant, and
the encapsulant is disposed on side surfaces of the lower portion of the dummy silicon chip.
16 . The semiconductor package of claim 13 , wherein the dummy silicon chip is bonded to the lower chip by using a thermally conductive adhesive layer.
17 . The semiconductor package of claim 13 , wherein:
the lower chip is bonded to the upper chip by using a hybrid bonding, and
the lower chip is stacked on the redistribution substrate by using a bump.
18 . A semiconductor package, comprising:
a redistribution substrate;
a stacked chip disposed on the redistribution substrate and comprising a lower chip and an upper chip;
a dynamic random access memory (DRAM) chip disposed on the redistribution substrate adjacent to the stacked chip;
a dummy silicon chip adjacent to the upper chip disposed on the lower chip;
an encapsulant encapsulating the stacked chip, the DRAM chip, and the dummy silicon chip on the redistribution substrate; and
an external connection terminal disposed under a lower surface of the redistribution substrate,
wherein an upper surface of the upper chip and an upper surface of the dummy silicon chip are exposed from the encapsulant, and
wherein at least a portion of side surfaces of the dummy silicon chip are exposed from the encapsulant.
19 . The semiconductor package of claim 18 , wherein:
the dummy silicon chip has at least one of a first structure having a substantially similar thickness and a second structure having an upper portion and a lower portion, and
a first thickness of the upper portion is smaller than a second thickness of the lower portion.
20 . The semiconductor package of claim 18 , wherein:
the lower chip is bonded to the upper chip by using a hybrid bonding, and
the dummy silicon chip is bonded to the lower chip by using a thermally conductive adhesive layer.