IP Library Granted Patent US 10,256,289
Granted Patent B2
US 10,256,289 · App. 15/805,829 · Granted Apr 9, 2019

Efficient metal-insulator-metal capacitor fabrication

Inventors: Kisup Chung (Albany, NY); Isabel C. Estrada-Raygoza (Albany, NY); Hemanth Jagannathan (Niskayuna, NY); Chi-Chun Liu (Altamont, NY); Yann A. M. Mignot (Slingerlands, NY); Hao Tang (Albany, NY)
Assignee: International Business Machines Corporation
H01L28/60
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,256,289
App. No.
15/805,829
Granted
Apr 9, 2019
Kind
B2
Abstract

Methods of forming capacitors include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.

Claims (23)

1. A method for forming a capacitor, comprising:

forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate that includes an embedded bottom contact;

etching away the second block copolymer material;

etching material from the substrate based on a pattern defined by the first block copolymer material to form a cavity in the substrate to a depth below a top surface of the embedded bottom contact; and

conformally depositing a capacitor stack over the substrate, such that the capacitor stack is formed in contact with the embedded bottom contact and vertical surfaces of the cavity.

2. The method of claim 1 , further comprising forming a mask over the capacitor stack to define a capacitor area and etching away the capacitor stack from areas that are not covered by the mask.

3. The method of claim 2 , further comprising forming a mask over the substrate before etching material from the substrate to limit an etched area.

4. The method of claim 3 , wherein forming the mask over the capacitor stack and forming the mask over the substrate comprise lithographically defining the respective masks using a same lithographic pattern and developers of opposite polarity.

5. The method of claim 1 , further comprising depositing a layer of dielectric material over the capacitor stack.

6. The method of claim 5 , forming a top conductive contact through the layer of dielectric material to contact the capacitor stack.

7. The method of claim 1 , wherein the first block copolymer material is polystyrene and the second block copolymer material is poly(methyl methacrylate).

8. A method for forming a capacitor, comprising:

forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate that includes an embedded bottom contact;

etching away the second block copolymer material;

forming a first mask over the substrate;

etching material from the substrate in an area exposed by the first mask and the first block copolymer material to form cavities in the substrate to a depth below a top surface of the embedded bottom contact;

conformally depositing a capacitor stack over the substrate, such that the capacitor stack is formed in contact with the bottom contact and vertical surfaces of the cavities;

forming a second mask over the capacitor stack to define a capacitor area, wherein a same lithographic pattern and a developer of opposite polarity is used to form the second mask as is used to form the first mask; and

etching away the capacitor stack from areas that are not covered by the second mask.

9. The method of claim 8 , further comprising depositing a protective layer over the capacitor stack before forming the second mask.

10. The method of claim 8 , further comprising depositing a layer of dielectric material over the capacitor stack.

11. The method of claim 10 , forming a top conductive contact through the layer of dielectric material to contact the capacitor stack.

12. The method of claim 8 , wherein the first block copolymer material is polystyrene and the second block copolymer material is poly(methyl methacrylate).

Assignments (6)
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0771 →
CHANGE OF NAME Recorded Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0868 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051493/0546 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY PREVIOUSLY RECORDED AT REEL: 044056 FRAME: 0022. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 9, 2019
From: CHUNG, KISUP; ESTRADA-RAYGOZA, ISABEL C.; JAGANNATHAN, HEMANTH; LIU, CHI-CHUN; MIGNOT, YANN A.M.; TANG, HAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 051225/0433 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2017
From: CHUNG, KISUP; ESTRADA-RAYGOZA, ISABEL C.; JAGANNATHAN, HEMANTH; LIU, CHI-CHUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044056/0022 →
Continuity (2)
Continuation 15462501 · Mar 17, 2017
Related Publication 20180269274A1 · Sep 20, 2018