Scalable semiconductor interposer integration

1. A method of forming an electronic package, the method comprising:

forming a first substrate, wherein the first substrate comprises a first plurality of through-substrate vias perpendicular to a first plane of the first substrate and passing through the entire thickness of the first substrate;

forming a second substrate having a second plane parallel to the first plane, wherein the second substrate comprises a second plurality of through-substrate vias perpendicular to the second plane of the second substrate and passing through the entire thickness of the second substrate;

positioning at least one standoff substrate between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of through-substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of through-substrate vias are electrically connected to a portion of the first plurality of through-substrate vias by way of a portion of the intervening plurality of through-substrate vias;

placing a plurality of electronic components within the clearance; and

electrically coupling the plurality of electronic components to the first substrate by a first plurality of electrical connections, wherein

the plurality of electronic components including a first electronic component and a second electronic component, and

the first electronic component is stacked on top of the second electronic component or the second electronic component is stacked on the first electronic component forming a stacked component.

2. The method of forming an electronic package according to claim 1 , wherein

one of the plurality of the electronic components is an antenna or amplifier or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or laser or FPGA or analog circuit or digital circuit or SerDes or filter or Lens or GPU or waveguide or fiber or accelerator or MEMS or heat spreader or RDL or an energy source such as battery.

3. The method of forming an electronic package according to claim 1 , wherein

all of said plurality of electronic components are the same type of component.

4. The method of forming an electronic package according to claim 1 , wherein

at least two of said plurality of electronic components are the same type of component.

5. The method of forming an electronic package according to claim 1 , wherein

the plurality of electronic components including the first electronic component, the second electronic component and a third electronic component, and

at least one of the first electronic component, the second electronic component or the third electronic component is stacked on the top of each other, forming a stacked component.

6. The method of forming an electronic package according to claim 5 , wherein

the first electronic component having a height surface area different from a height surface area of the second electronic component,

said height surface area of the first electronic component is different from a height surface area of the third electronic component, and

said height surface area of the second electronic component is different from the height surface area of the third electronic component.

7. The method of forming an electronic package according to claim 5 , wherein the first electronic component, the second electronic component and the third electronic component communicate through Redistribution Layer (RDL).

8. The method of forming an electronic package according to claim 1 , wherein

the first substrate and/or second substrate contains one or more cavities and/or through holes.

9. The method of forming an electronic package according to claim 1 , wherein

at least one of said plurality of electronic components is electrically coupled to at least one standoff substrate.

10. The method of forming an electronic package according to claim 1 , wherein

at least one standoff substrate and at least one substrate is manufactured as one piece.

11. The method of forming an electronic package according to claim 1 , wherein

at least one substrate and at least one electronic component is manufactured as one piece.

12. The method of forming an electronic package according to claim 1 , wherein

at least one substrate comprises of RDL.

13. The method of forming an electronic package according to claim 11 , wherein

at least one substrate comprises of RDL.

14. An electronic package comprising:

a first substrate, wherein the first substrate comprises a first plurality of through-substrate vias perpendicular to a first plane of the first substrate and passing through the entire thickness of the first substrate;

a second substrate having a second plane parallel to the first plane, wherein the second substrate comprises a second plurality of through-substrate vias perpendicular to the second plane of the second substrate and passing through the entire thickness of the second substrate;

at least one standoff substrate positioned between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of through-substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of through-substrate vias are electrically connected to a portion of the first plurality of through-substrate vias by way of a portion of the intervening plurality of through-substrate vias; and

a plurality of electronic components located within the clearance, wherein

the plurality of electronic components is electrically coupled to the first substrate by a first plurality of electrical connections,

the plurality of electronic components including a first electronic component and a second electronic component,

the first electronic component and the second electronic component each being one of either a processor, a memory or a sensor, and

the first electronic component is a different electronic component as compared to the second electronic component.

15. The electronic package according to claim 14 , wherein

one of the plurality of the electronic components is an antenna or amplifier or FPGA or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or laser or analog circuit or digital circuit or SerDes or filter or Lens or GPU or waveguide or fiber or accelerator or MEMS or heat spreader or RDL or an energy source such as battery.

16. The electronic package according to claim 15 , wherein

at least one of said plurality of electronic components is electrically coupled to the first substrate and/or second substrate.

17. The electronic package according to claim 14 , wherein

the first substrate and/or second substrate contains one or more cavities and/or through holes.

18. The electronic package according to claim 14 , wherein

the plurality of electronic components including the first electronic component, the second electronic component and a third electronic component,

the first electronic component, the second electronic component and the third electronic component is one of either the processor, the memory or the sensor, and

the third electronic component is a different electronic component as compared to the first electronic component and the second electronic component.

19. The electronic package according to claim 18 , wherein

the first electronic component having a height surface area different from a height surface area of the second electronic component,

said height surface area of the first electronic component is different from a height surface area of the third electronic component, and

said height surface area of the second electronic component is different from the height surface area of the third electronic component.

20. The electronic package according to claim 18 , wherein

the first electronic component, the second electronic component and the third electronic component communicate through Redistribution Layer (RDL).

21. The electronic package according to claim 14 , wherein

at least two of said plurality of electronic components are the same type of component.

22. The electronic package according to claim 14 , wherein

at least one of said plurality of electronic components is electrically coupled to at least one standoff substrate.

23. The electronic package according to claim 14 , wherein

at least one standoff substrate and at least one substrate is manufactured as one piece.

24. The electronic package according to claim 14 , wherein

at least one substrate and at least one electronic component is manufactured as one piece.

25. The electronic package according to claim 14 , wherein

at least one substrate comprises of RDL.

26. The electronic package according to claim 24 , wherein

at least one substrate comprises of RDL.

27. A method of forming an electronic package, the method comprising:

forming a first substrate, wherein the first substrate comprises a first plurality of through-substrate vias perpendicular to a first plane of the first substrate and passing through the entire thickness of the first substrate;

forming a second substrate having a second plane parallel to the first plane, wherein the second substrate comprises a second plurality of through-substrate vias perpendicular to the second plane of the second substrate and passing through the entire thickness of the second substrate;

positioning at least one standoff substrate between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of through-substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of through-substrate vias are electrically connected to a portion of the first plurality of through-substrate vias by way of a portion of the intervening plurality of through-substrate vias;

placing a plurality of electronic components within the clearance; and

coupling the plurality of electronic components to the first substrate, wherein

the plurality of electronic components including a first electronic component and a second electronic component,

the plurality of electronic components including the first electronic component, the second electronic component, and a third electronic component, and

at least one of the first electronic component, the second electronic component or the third electronic component is stacked on the top of each other.

28. The method of forming an electronic package according to claim 27 , wherein

all of said plurality of electronic components are the same type of component.

29. The method of forming an electronic package according to claim 27 , wherein

at least two of said plurality of electronic components are the same type of component.

30. An electronic package comprising:

a first substrate, wherein the first substrate comprises a first plurality of through-substrate vias perpendicular to a first plane of the first substrate and passing through the entire thickness of the first substrate;

a second substrate having a second plane parallel to the first plane, wherein the second substrate comprises a second plurality of through-substrate vias perpendicular to the second plane of the second substrate and passing through the entire thickness of the second substrate;

at least one standoff substrate positioned between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of through-substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of through-substrate vias are electrically connected to a portion of the first plurality of through-substrate vias by way of a portion of the intervening plurality of through-substrate vias;

a plurality of electronic components located within the clearance; and

the plurality of electronic components is coupled to the first substrate, wherein

the plurality of electronic components including a first electronic component and a second electronic component,

the plurality of electronic components including the first electronic component, the second electronic component, and a third electronic component, and

at least one of the first electronic component, the second electronic component or the third electronic component is stacked on the top of each other.

31. The electronic package according to claim 30 ,

all of said plurality of electronic components are the same type of component.

32. The electronic package according to claim 30 , wherein

at least two of said plurality of electronic components are the same type of component.

33. The electronic package according to claim 30 , wherein

one of the plurality of the electronic components is an antenna or amplifier or FPGA or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-fill or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.

34. The electronic package according to claim 30 , wherein

the first substrate and/or second substrate contains one or more cavities and/or through holes.

35. The electronic package according to claim 30 , wherein

at least one of said plurality of electronic components is coupled to at least one standoff substrate.

36. The electronic package according to claim 30 , wherein

at least one substrate and at least one electronic component is manufactured as one piece.

37. The electronic package according to claim 30 , wherein

at least one substrate comprises of RDL.

38. The electronic package according to claim 36 , wherein

at least one substrate comprises of RDL.

39. The electronic package according to claim 30 , wherein

at least one of the plurality of electronic component is coupled to the first substrate and/or second substrate and/or standoff substrate.

40. A method of forming an electronic package, the method comprising:

forming a first substrate, wherein the first substrate comprises a first plurality of substrate vias;

forming a second substrate, wherein the second substrate comprises a second plurality of substrate vias;

positioning at least one standoff substrate between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of substrate vias are coupled to a portion of the first plurality of substrate vias by way of a portion of the intervening plurality of substrate vias;

placing a plurality of electronic components within the clearance; and

coupling the plurality of electronic components to the first substrate, wherein

the plurality of electronic components including a first electronic component and a second electronic component, and

the first electronic component is stacked on top of the second electronic component or the second electronic component is stacked on the first electronic component forming a stacked component.

41. The method of forming an electronic package according to claim 40 , wherein

one of the plurality of the electronic components is an antenna or amplifier or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or FPGA or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-full or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.

42. The method of forming an electronic package according to claim 40 , wherein

all of said plurality of electronic components are the same type of component.

43. The method of forming an electronic package according to claim 40 , wherein

at least two of said plurality of electronic components are the same type of component.

44. The method of forming an electronic package according to claim 40 , wherein

the first substrate and/or second substrate contains one or more cavities and/or through holes.

45. The method of forming an electronic package according to claim 40 , wherein

at least one of said plurality of electronic components is coupled to at least one standoff substrate.

46. The method of forming an electronic package according to claim 40 , wherein

at least one substrate and at least one electronic component is manufactured as one piece.

47. The method of forming an electronic package according to claim 40 , wherein

at least one substrate comprises of RDL.

48. The method of forming an electronic package according to claim 46 , wherein

at least one substrate comprises of RDL.

49. The method of forming an electronic package according to claim 40 , wherein

at least one of the plurality of electronic component is coupled to the first substrate and/or second substrate and/or standoff substrate.

50. An electronic package comprising:

a first substrate, wherein the first substrate comprises a first plurality of substrate vias;

a second substrate wherein the second substrate comprises a second plurality of substrate vias;

at least one standoff substrate positioned between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of substrate vias are coupled to a portion of the first plurality of substrate vias by way of a portion of the intervening plurality of substrate vias; and

a plurality of electronic components located within the clearance, wherein

the plurality of electronic components is coupled to the first substrate,

the plurality of electronic components including a first electronic component and a second electronic component,

the first electronic component and the second electronic component each being one of either a processor, a memory or a sensor, and

the first electronic component is a different electronic component as compared to the second electronic component.

51. The electronic package according to claim 50 , wherein

one of the plurality of the electronic components is an antenna or amplifier or FPGA or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-full or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.

52. The electronic package according to claim 51 , wherein

one of the plurality of electronic component is coupled to the first substrate and/or second substrate and/or standoff substrate and/or other electronic components.

53. The electronic package according to claim 50 , wherein

all of said plurality of electronic components are the same type of component.

54. The electronic package according to claim 50 , wherein

at least two of said plurality of electronic components are the same type of component.

55. The electronic package according to claim 50 , wherein

the first substrate and/or second substrate contains one or more cavities and/or through holes.

56. The electronic package according to claim 50 , wherein

at least one of said plurality of electronic components is coupled to at least one standoff substrate.

57. The electronic package according to claim 50 , wherein

at least one substrate and at least one electronic component is manufactured as one piece.

58. The electronic package according to claim 50 , wherein

at least one substrate comprises of RDL.

59. The electronic package according to claim 57 , wherein

at least one substrate comprises of RDL.

60. The electronic package according to claim 50 , wherein

at least one of the plurality of electronic component is coupled to the first substrate and/or second substrate and/or standoff substrate.