IP Library Granted Patent US 10,326,013
Granted Patent B2
US 10,326,013 · App. 15/819,822 · Granted Jun 18, 2019

Method of forming a field-effect transistor (FET) or other semiconductor device with front-side source and drain contacts

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Quick Facts
Patent No.
US 10,326,013
App. No.
15/819,822
Granted
Jun 18, 2019
Kind
B2
Abstract

A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain contacts. The method may include forming an epitaxy region, forming a poly gate trench in the epitaxy region, forming a drain contact trench through the poly gate trench and extending below the poly gate trench, forming a poly gate in the poly gate trench, forming a front-side drain contact in the drain contact trench, and forming a source region in the epitaxy region adjacent the poly gate. The device may define a drift region from the poly gate/source intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extending into an underlying substrate or transition layer. The front-side drain contact depth may be selected to influence the device breakdown voltage. The front-side drain contacts may allow flip-chip mounting of the IC structure.

Claims (36)

1. A method of forming a semiconductor device, the method comprising:

forming an epitaxy region;

forming a poly gate trench in the epitaxy region;

forming a drain contact trench through the poly gate trench and extending downwardly to a further vertical depth in the epitaxy region than the poly gate trench;

forming a poly gate in the poly gate trench after forming the drain contact trench;

forming a gate contact contiguous with the poly gate and extending laterally over the epitaxy region in a direction away from the poly gate trench;

forming a front-side drain contact in the drain contact trench, wherein the front-side drain contact extends downwardly to a further vertical depth than the poly gate, but only partially through a vertical depth of the epitaxy region, such that a bottom of the front-side drain contact is located above and spaced-apart from a bottom surface of the epitaxy region; and

forming a source region in the epitaxy region adjacent the poly gate;

wherein a drift region extending from an intersection of the poly gate and source region to the bottom of front-side drain contact is fully contained within the epitaxy region.

2. The method of claim 1 , wherein the front-side drain contact in the drain contact trench is isolated from each of the at least one poly gate by a respective insulating spacer.

3. The method of claim 1 , comprising:

forming a bulk substrate; and

forming the epitaxy region over the bulk substrate;

wherein the drift region does not extend into the bulk substrate.

4. The method of claim 3 , comprising forming the epitaxy region direct on the bulk substrate such that the epitaxy region is directly coupled to the bulk substrate.

5. The method of claim 1 , comprising:

forming a bulk substrate; and

forming or defining a transition region between the epitaxy region and the bulk substrate;

wherein the drift region does not extend into the transition region.

6. The method of claim 1 , comprising:

forming a pair of poly gates in the poly gate trench;

forming the front-side drain contact in the drain contact trench such that the front-side drain contact extends between the pair of poly gates in the poly gate trench.

7. The method of claim 6 , comprising forming a respective insulating spacer between the front-side drain contact and each of the pair of poly gates.

8. The method of claim 1 , wherein the semiconductor device comprises a trench field-effect transistor (FET).

9. A method of forming a semiconductor device, the method comprising:

forming an epitaxy region;

forming a poly gate trench in the epitaxy region;

depositing a sacrificial layer that extends into the poly gate trench to define sacrificial sidewalls in the poly gate trench;

forming a drain contact trench through an opening defined between the sacrificial sidewalls in the poly gate trench and extending downwardly to a further depth in the epitaxy region than the poly gate trench;

filling the drain contact trench with a drain contact trench fill material;

removing the sacrificial sidewalls in the poly gate trench to define poly gate openings in the poly gate trench;

filling the poly gate openings with poly gate material to form poly gates in the poly gate trench;

etching a drain contact opening in the drain contact trench fill material; and

filling the drain contact opening with drain contact material to form a front-side drain contact in the drain contact trench, wherein the front-side drain contact is contained in the epitaxy region; and

forming a source region in the epitaxy region adjacent the poly gate;

wherein a drift region is defined from an intersection of the poly gate and source region to the front-side drain contact.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2017
From: DIX, GREG; SHUMATE, JINA; PETERSON, ERIC; NAYAK, RAJESH
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 044675/0048 →