Protocol analysis and visualization during simulation
Protocol analysis can include simulating, using a processor, a circuit design including a protocol analyzer embedded therein. The protocol analyzer can be coupled to low-level signals of an interface of the circuit design. During the simulating, the protocol analyzer detects a transaction from the low-level signals received from the interface. Transaction data is generated by the protocol analyzer specifying the transaction. The transaction data is output from the protocol analyzer.
1. A method for protocol analysis, comprising:
incorporating, using a processor, a protocol analyzer into a circuit design through compilation, wherein the protocol analyzer is coupled to low-level signals of an interface of the circuit design from the compilation, wherein the interface includes an on-chip bus interface connecting two modules of the circuit design;
simulating, using the processor executing a simulator, the circuit design including the protocol analyzer embedded therein;
during the simulating, the protocol analyzer detecting a transaction on the bus from the low-level signals of the bus;
during the simulating, the protocol analyzer generating transaction data specifying the transaction and including, within the transaction data, an instruction specifying formatting for presenting the transaction in a viewer; and
outputting, from the protocol analyzer and the simulator, the transaction data.
2. The method of claim 1 , wherein the circuit design is specified in a hardware description language.
3. The method of claim 1 , wherein the transaction data is generated directly from the low-level signals during the simulating.
4. The method of claim 1 , wherein the detecting the transaction from the low-level signals comprises:
determining a start of the transaction and a corresponding end of the transaction from the low-level signals.
5. The method of claim 1 , further comprising:
the viewer, executed by the processor, receiving the transaction data and displaying a waveform representing the transaction.
6. The method of claim 5 , further comprising:
the protocol analyzer including a transaction detail for the transaction within the transaction data during the simulating;
wherein the viewer displays the transaction detail in response to a request for additional information for the transaction.
7. The method of claim 1 , wherein the viewer is executable to display the transaction according to the instruction.
8. The method of claim 1 , wherein the incorporating the protocol analyzer into the circuit design through compilation generates executable program code from the circuit design.
9. A system for protocol analysis, comprising:
a processor configured to initiate operations including:
incorporating a protocol analyzer into a circuit design through compilation, wherein the protocol analyzer is coupled to low-level signals of an interface of the circuit design from the compilation, wherein the interface includes an on-chip bus interface connecting two modules of the circuit design;
simulating, by executing a simulator, the circuit design including the protocol analyzer embedded therein;
during the simulating, the protocol analyzer detecting a transaction from the low-level signals of the bus;
during the simulating, the protocol analyzer generating transaction data specifying the transaction and including, within the transaction data, an instruction specifying formatting for presenting the transaction in a viewer; and
outputting, from the protocol analyzer and the simulator, the transaction data.
10. The system of claim 9 , wherein the circuit design is specified in a hardware description language.
11. The system of claim 9 , wherein the transaction data is generated directly from the low-level signals during the simulating.
12. The system of claim 9 , wherein the detecting the transaction from the low-level signals comprises:
determining a start of the transaction and a corresponding end of the transaction from the low-level signals.
13. The system of claim 9 , further comprising:
a display device, wherein the viewer is executable by the processor to receive the transaction data and display a waveform representing the transaction on the display device.
14. The system of claim 13 , wherein:
the protocol analyzer is configured to include a transaction detail for the transaction within the transaction data during the simulating; and
the viewer displays the transaction detail on the display device in response to a request for additional information for the transaction.
15. The system of claim 9 , wherein the viewer is executable to display the transaction according to the instruction.
16. A computer program product comprising a computer readable storage medium having program code stored thereon, the program code executable by a processor to perform operations for protocol analysis, the operations comprising:
incorporating a protocol analyzer into a circuit design through compilation, wherein the protocol analyzer is coupled to low-level signals of an interface of the circuit design from the compilation, wherein the interface includes an on-chip bus interface connecting two modules of the circuit design;
simulating, using the processor executing a simulator, the circuit design including the protocol analyzer embedded therein;
during the simulating, the protocol analyzer detecting a transaction on the bus from the low-level signals of the bus;
during the simulating, the protocol analyzer generating transaction data specifying the transaction and including, within the transaction data, an instruction specifying formatting for presenting the transaction in a viewer; and
outputting, from the protocol analyzer and the simulator, the transaction data.