Framework for system simulation using multiple simulators
A simulation framework is capable of modeling a hardware implementation of a reference software system using models specified in different computer-readable languages. The models correspond to different ones of a plurality of subsystems of the hardware implementation. Input data is provided to a first simulator configured to simulate a first model of a first subsystem of the modeled hardware implementation. The input data is captured from execution of the reference software system. The first simulator executing the first model generates a first data file specifying output of the first subsystem. The first data file specifies intermediate data of the modeled hardware implementation. The first data file is provided to a second simulator configured to simulate a second model of a second subsystem of the modeled hardware implementation. The second simulator executing the second model generates a second data file specifying output of the second subsystem.
1 . A method, comprising:
modeling a hardware implementation of a reference software system using models that correspond to different ones of a plurality of subsystems of the hardware implementation;
simulating, by a first simulator, an executable model of a first subsystem of the plurality of subsystems that implements a protocol processor configured to classify packets of input data as normal packets forwarded directly to a host data processing system and block chain packets requiring further processing by the hardware implementation;
generating, from the first simulator executing the executable model, a first data file specifying output of the first subsystem, wherein the first data file specifies intermediate data generated by the executable model;
simulating, by a second simulator, a register transfer level model of a second subsystem of the plurality of subsystems that implements a block processor coupled to the protocol processor and configured to implement block and transaction verification operations on the first data file; and
generating, from the second simulator executing the register transfer level model, a second data file specifying output of the second subsystem;
wherein the first data file and the second data file are specified in human-readable text.
2 . The method of claim 1 , wherein the hardware implementation is a network-attached accelerator.
3 . The method of claim 2 , wherein the hardware implementation is configured to perform blockchain transaction processing.
4 . The method of claim 1 , wherein at least one of the first data file or the second data file specifies particular ports of the hardware implementation over which data specified by the first data file or the second data file is conveyed.
5 . The method of claim 1 , further comprising:
capturing output data generated by the reference software system;
comparing the second data file with the output data; and
determining whether the hardware implementation behaves as designed based on the comparing.
6 . The method of claim 1 , further comprising:
editing at least one of the first data file or the second data file by removing one or more blocks therein and editing a hash value and a block identifier to be consistent with the removing of the one or more blocks.
7 . The method of claim 1 , wherein at least one of the first data file or the second data file is encoded to specify data at a selected layer of an Open Systems Interconnect (OSI) model.
8 . A system, comprising:
a processor configured to initiate operations including:
modeling a hardware implementation of a reference software system using models that correspond to different ones of a plurality of subsystems of the hardware implementation;
simulating, by a first simulator, an executable model of a first subsystem of the plurality of subsystems that implements a protocol processor configured to classify packets of input data as normal packets forwarded directly to a host data processing system and block chain packets requiring further processing by the hardware implementation;
generating, from the first simulator executing the executable model, a first data file specifying output of the first subsystem, wherein the first data file specifies intermediate data generated by the executable model;
simulating, by a second simulator, a register transfer level model of a second subsystem of the plurality of subsystems that implements a block processor coupled to the protocol processor and configured to implement block and transaction verification operations on the first data file; and
generating, from the second simulator executing the register transfer level model, a second data file specifying output of the second subsystem;
wherein the first data file and the second data file are specified in human-readable text.
9 . The system of claim 8 , wherein the hardware implementation is a network-attached accelerator.
10 . The system of claim 9 , wherein the hardware implementation is configured to perform blockchain transaction processing.
11 . The system of claim 8 , wherein at least one of the first data file or the second data file specifies particular ports of the hardware implementation over which data specified by the first data file or the second data file is conveyed.
12 . The system of claim 8 , wherein the processor is further configured to initiate operations comprising:
capturing output data generated by the reference software system;
comparing the second data file with the output data; and
determining whether the hardware implementation behaves as designed based on the comparing.
13 . The system of claim 8 , wherein the processor is further configured to initiate operations comprising:
editing at least one of the first data file or the second data file by removing one or more blocks therein and editing a hash value and a block identifier to be consistent with the removing of the one or more blocks.
14 . The system of claim 8 , wherein at least one of the first data file or the second data file is encoded to specify data at a selected layer of an Open Systems Interconnect (OSI) model.
15 . A computer program product, comprising:
one or more computer-readable storage media, and program instructions collectively stored on the one or more computer-readable storage media, wherein the program instructions are executable by computer hardware to initiate operations including:
modeling a hardware implementation of a reference software system using models that correspond to different ones of a plurality of subsystems of the hardware implementation;
simulating, by a first simulator, an executable model of a first subsystem of the plurality of subsystems that implements a protocol processor configured to classify packets of input data as normal packets forwarded directly to a host data processing system and block chain packets requiring further processing by the hardware implementation;
generating, from the first simulator executing the executable model, a first data file specifying output of the first subsystem, wherein the first data file specifies intermediate data generated by the executable model;
simulating, by a second simulator, a register transfer level model of a second subsystem of the plurality of subsystems that implements a block processor coupled to the protocol processor and configured to implement block and transaction verification operations on the first data file; and
generating, from the second simulator executing the register transfer level model, a second data file specifying output of the second subsystem;
wherein the first data file and the second data file are specified in human-readable text.
16 . The computer program product of claim 15 , wherein the hardware implementation is a network-attached accelerator.
17 . The computer program product of claim 16 , wherein the hardware implementation is configured to perform blockchain transaction processing.
18 . The computer program product of claim 15 , wherein at least one of the first data file or the second data file specifies particular ports of the hardware implementation over which data specified by the first data file or the second data file is conveyed.
19 . The computer program product of claim 15 , wherein the program instructions are executable by the computer hardware to initiate operations including:
capturing output data generated by the reference software system;
comparing the second data file with the output data; and
determining whether the hardware implementation behaves as designed based on the comparing.
20 . The computer program product of claim 15 , wherein at least one of the first data file or the second data file is encoded to specify data at a selected layer of an Open Systems Interconnect (OSI) model.