Using implemented core sources for simulation

1. A method of using pin planning for core sources, comprising:

processing, using a processor, a circuit design including a core source through at least part of a design flow that includes a pin planning operation, wherein the core source includes a register transfer level description of circuitry having a first pin configuration;

comparing, using the processor, the first pin configuration of the core source with a second pin configuration of the core source subsequent to performing the at least part of the design flow;

responsive to detecting a difference between the first pin configuration and the second pin configuration from the comparing, automatically updating, using the processor, the core source by updating a portion of the first pin configuration with a portion of the second pin configuration that differed from the first pin configuration;

wherein the updating includes replacing a pin dependent portion of the core source specifying the first pin configuration with an updated pin dependent portion of the core source specifying the second pin configuration; and

performing behavioral simulation of the circuit design using the updated core source;

wherein the core source corresponds to a memory interface, a pin independent portion of the core source corresponds to a memory controller of the memory interface, and the pin dependent portion corresponds to a physical interface of the memory interface.

2. The method of claim 1 , wherein the behavioral simulation of the circuit design using the updated core source correlates with the circuit design subsequent to performing the design flow as implemented within an integrated circuit.

3. The method of claim 1 , wherein the comparing comprises:

determining whether an assignment of a node to a pin of a target integrated circuit has changed from the first pin configuration to the second pin configuration.

4. The method of claim 3 , wherein the pin is an external pin of the target integrated circuit.

5. The method of claim 3 , wherein the pin is an internal pin of the target integrated circuit.

6. The method of claim 1 , wherein the at least part of a design flow includes synthesis.

7. The method of claim 1 , wherein the at least part of a design flow includes placement.

8. A system for using pin planning for core sources, comprising:

a processor configured to initiate executable operations including:

processing a circuit design including a core source through at least part of a design flow that includes a pin planning operation, wherein the core source includes a register transfer level description of circuitry having a first pin configuration;

comparing the first pin configuration of the core source with a second pin configuration of the core source subsequent to performing the at least a part of the design flow;

responsive to detecting a difference between the first pin configuration and the second pin configuration from the comparing, automatically updating the core source by updating a portion of the first pin configuration with a portion of the second pin configuration that differed from the first pin configuration;

wherein the updating includes replacing a pin dependent portion of the core source specifying the first pin configuration with an updated pin dependent portion of the core source specifying the second pin configuration; and

performing behavioral simulation of the circuit design using the updated core source;

wherein the core source corresponds to a memory interface, a pin independent portion of the core source corresponds to a memory controller of the memory interface, and the pin dependent portion corresponds to a physical interface of the memory interface.

9. The system of claim 8 , wherein the behavioral simulation of the circuit design using the updated core source correlates with the circuit design subsequent to performing the design flow as implemented within an integrated circuit.

10. The system of claim 8 , wherein the comparing comprises:

determining whether an assignment of a node to a pin of a target integrated circuit has changed from the first pin configuration to the second pin configuration.

11. The system of claim 10 , wherein the pin is an external pin of the target integrated circuit.

12. The system of claim 10 , wherein the pin is an internal pin of the target integrated circuit.

13. The system of claim 8 , wherein the at least part of a design flow includes synthesis.

14. The system of claim 8 , wherein the at least part of a design flow includes placement.

15. A computer program product comprising a computer readable storage medium having program code stored thereon, the program code executable by a processor to perform operations for using pin planning for core sources, comprising:

processing, using the processor, a circuit design including a core source through at least part of a design flow that includes a pin planning operation, wherein the core source includes a register transfer level description of circuitry having a first pin configuration;

comparing, using the processor, the first pin configuration of a core source with the second pin configuration of the core source subsequent to performing the at least a part of the design flow;

responsive to detecting a difference between the first pin configuration and the second pin configuration from the comparing, automatically updating, using the processor, the core source by updating a portion of the first pin configuration with a portion of the second pin configuration that differed from the first pin configuration; and

wherein the updating includes replacing a pin dependent portion of the core source specifying the first pin configuration with an updated pin dependent portion of the core source specifying the second pin configuration; and

performing behavioral simulation of the circuit design using the updated core source;

wherein the core source corresponds to a memory interface, a pin independent portion of the core source corresponds to a memory controller of the memory interface, and the pin dependent portion corresponds to a physical interface of the memory interface.

16. The computer program product of claim 15 , wherein the behavioral simulation of the circuit design using the updated core source correlates with the circuit design subsequent to performing the design flow as implemented within an integrated circuit.

17. The computer program product of claim 15 , wherein the comparing comprises:

determining whether an assignment of a node to a pin of a target integrated circuit has changed from the first pin configuration to the second pin configuration.

18. The computer program product of claim 17 , wherein the pin is an external pin of the target integrated circuit or an internal pin of the target integrated circuit.

19. The computer program product of claim 15 , wherein the at least part of a design flow includes synthesis.

20. The computer program product of claim 15 , wherein the at least part of a design flow includes placement.