III-Nitride transistor including a III-N depleting layer

1. A transistor, comprising:

a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a III-N depleting layer, wherein the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer;

a source and a drain, each of which being directly connected to the III-N channel layer;

a gate between the source and the drain, the gate being over the III-N layer structure, wherein the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; wherein

the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

2. The transistor of claim 1 , further comprising a field plate which directly contacts the first portion of the III-N depleting layer and is electrically connected to the source.

3. The transistor of claim 2 , having a threshold voltage, wherein

mobile charge in the 2DEG channel in the access region between the gate and the drain is depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased above a minimum voltage relative to the source, but not depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased below the minimum voltage relative to the source, and

the minimum voltage is in a range of 20V to 100V.

4. The transistor of claim 1 , wherein

the III-N depleting layer further comprises a second portion disposed in a device access region between the source and the gate,

the transistor further comprises a recess extending through, and separating the first and second portions of the III-N depleting layer, and

the gate is in the recess.

5. The transistor of claim 4 , wherein the recess extends at least partially through the III-N channel layer.

6. The transistor of claim 5 , wherein the transistor further comprises an insulating layer, the insulating layer being between the gate and the III-N layer structure.

7. The transistor of claim 6 , wherein the transistor is an enhancement mode transistor.

8. The transistor of claim 1 , wherein the III-N layer structure is oriented in an N-polar direction, and the gate is over an N-face of the III-N layer structure.

9. The transistor of claim 1 , wherein the III-N depleting layer includes a superlattice comprising alternating p-doped III-N layers and un-doped III-N layers.

10. The transistor of claim 1 , wherein the III-N depleting layer includes a superlattice comprising alternating III-N layers of varying bandgap or composition.

11. The transistor of claim 1 , wherein the III-N depleting layer includes a superlattice comprising alternating layers of GaN and AlGaN.

12. A transistor, comprising:

a III-N channel layer;

a III-N barrier layer, wherein the III-N channel layer includes a 2DEG channel adjacent an interface between the III-N channel layer and the III-N barrier layer;

a source and a drain, each of which being directly connected to the III-N channel layer;

a gate between the source and the drain, the gate being over the 2DEG channel;

a III-N depleting layer disposed in a device access region between the gate and the drain; and

a field plate that is electrically connected to the source and to the III-N depleting layer, and is electrically isolated from the gate,

wherein the III-N depleting layer is electrically isolated from the drain.

13. The transistor of claim 12 , wherein

the transistor is configured such that mobile charge in the 2DEG channel in the access region between the gate and the drain is depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased above a minimum voltage relative to the source, but not depleted while the gate is biased relative to the source at a voltage lower than the threshold voltage and the drain is biased below the minimum voltage relative to the source, and

the minimum voltage is in a range of 20V to 100V.

14. The transistor of claim 12 , wherein

the III-N depleting layer has a portion disposed in a device access region between the source and the gate, and

the transistor further comprises a recess extending through the III-N depleting layer, such that the gate is in the recess.

15. The transistor of claim 14 , wherein the recess extends at least partially through the III-N channel layer.

16. The transistor of claim 15 , wherein the transistor further comprises an insulating layer, the insulating layer being between the gate and the III-N layer structure.

17. The transistor of claim 16 , wherein the transistor is an enhancement mode transistor.

18. The transistor of claim 12 , wherein

a III-N layer structure including the III-N channel layer, the III-N barrier layer and the III-N depleting layer is oriented in an N-polar direction, and

the gate is over an N-face of the III-N layer structure.

19. The transistor of claim 12 , wherein the III-N depleting layer includes a superlattice comprising alternating p-doped III-N layers and un-doped III-N layers.

20. The transistor of claim 12 , wherein the III-N depleting layer includes a superlattice comprising alternating layers of GaN and AlGaN.