Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same

1. A method of forming an integrated circuit structure, the method comprising:

providing a substrate having a front side and a back side, the substrate including:

a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate,

etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side;

forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and

forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

2. The method of claim 1 , wherein the forming of the TSV includes:

forming a mask covering the first dielectric layer over the back side of the substrate and extending away from the front side of the substrate;

patterning the mask to expose the first dielectric layer over the back side of the substrate;

forming an opening through the first dielectric layer toward the front side of the wafer to expose a back-end-of-the-line (BEOL) region on the front side of the substrate;

extending the opening through the BEOL region toward the front side of the substrate to expose a first handle wafer;

forming a first liner layer within the opening to substantially coat the opening; and

forming a first metal over the first liner layer to substantially fill the opening.

3. The method of claim 1 , further comprising:

forming a wire within the first dielectric layer during the forming of the first dielectric layer, the wire including a first liner layer and a first metal over the first liner layer prior to the forming of the TSV.

4. The method of claim 3 , wherein the forming of the TSV includes forming the TSV such that the TSV is adjacent to and separated from the wire in the first dielectric layer.

5. The method of claim 3 , wherein the forming of the wire includes forming the wire in a position within the first dielectric layer that is adjacent to an anticipated position of the TSV.

6. The method of claim 3 , further comprising:

forming a connection extending from wire away from the front side of the substrate to a surface of the dielectric layer that is farthest from the front side of the substrate; and

forming a conductive pad over the TSV, the connection, and at least a portion of the dielectric layer such that the wire is electrically connected to the TSV by the connection and the conductive pad.

7. The method of claim 1 , further comprising:

forming a conductive pad over the back side of the substrate extending away from the front side of the substrate after the forming of the first dielectric layer, the conductive pad covering a portion of the first dielectric layer and the TSV.

8. The method of claim 7 , further comprising:

forming a second dielectric layer covering the conductive pad and the first dielectric layer over the back side of the substrate extending away from the front side of the substrate.

9. The method of claim 8 , further comprising:

forming a connection within the second dielectric layer connected to the conductive pad and extending away from the front side of the substrate.

10. The method of claim 1 , wherein the forming of the first dielectric layer includes forming a polymer.

11. The method of claim 1 , further comprising:

forming a first handle wafer on the front side of the substrate covering a back-end-of-the-line (BEOL) region and extending away from the back side of the substrate after the providing of the substrate and prior to the etching of the substrate on the back side of the substrate; and

removing the first handle substrate from the front side of the substrate after the forming of the TSV.