Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.
1. A method for making a CMOS image sensor comprising:
forming a first semiconductor chip comprising an array of image sensor pixels and readout circuitry electrically connected thereto;
forming a second semiconductor chip comprising image processing circuitry to be electrically connected to the readout circuitry; and
coupling the first semiconductor chip and the second semiconductor chip together in a stack;
the readout circuitry comprising a plurality of transistors each comprising
spaced apart source and drain regions,
a superlattice channel extending between the source and drain regions, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
a gate comprising a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer;
wherein a superlattice is not located within the image processing circuitry.
2. The method of claim 1 wherein forming the first semiconductor chip further comprises forming an electrical interconnect layer beneath the array of image sensor pixels and defining a back side illumination (BSI) configuration therewith, the electrical interconnect layer electrically connecting the array of image sensor pixels with the readout circuitry.
3. The method of claim 2 wherein forming the electrical interconnect layer comprises forming a semiconductor layer and a plurality of spaced apart conductive traces within the semiconductor layer.
4. The method of claim 1 further comprising positioning at least one lens overlying the array of image sensor pixels.
5. The method of claim 1 further comprising positioning at least one color filter overlying the array of image sensor pixels.
6. The method of claim 5 wherein the at least one color filter comprises a respective color filter for each of the pixels in the array of image sensor pixels.
7. The method of claim 5 wherein the at least one color filter comprises a plurality of different color filters for filtering different respective wavelengths of light.
8. The method of claim 1 further comprising forming a third semiconductor chip comprising a plurality of memory circuits; and wherein coupling further comprises coupling the third semiconductor chip with the first and second semiconductor chips in the stack.
9. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.
10. The method of claim 1 wherein the semiconductor monolayers comprise silicon.
11. A method for making a CMOS image sensor comprising:
forming a first semiconductor chip comprising an array of image sensor pixels, an electrical interconnect layer beneath the array of image sensor pixels and defining a back side illumination (BSI) configuration therewith, and readout circuitry electrically connected to the array of image sensor pixels by the electrical interconnect layer;
forming a second semiconductor chip comprising image processing circuitry electrically to be connected to the readout circuitry;
forming a third semiconductor chip comprising a plurality of memory circuits; and
coupling the first, second and third semiconductor chips together in a stack;
the readout circuitry comprising a plurality of transistors each comprising
spaced apart source and drain regions,
a superlattice channel extending between the source and drain regions, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and
a gate comprising a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer;
wherein a superlattice is not located within the image processing circuitry.
12. The method of claim 11 further comprising positioning at least one lens overlying the array of image sensor pixels.
13. The method of claim 11 further comprising positioning at least one color filter overlying the array of image sensor pixels.
14. The method of claim 11 wherein the at least one non-semiconductor monolayer comprises oxygen.
15. The method of claim 11 wherein the semiconductor monolayers comprise silicon.
16. A method for making a CMOS image sensor comprising:
forming a first semiconductor chip comprising an array of image sensor pixels and readout circuitry electrically connected thereto;
forming a second semiconductor chip comprising image processing circuitry to be electrically connected to the readout circuitry; and
coupling the first semiconductor chip and the second semiconductor chip together in a stack;
the readout circuitry comprising a plurality of transistors each comprising
spaced apart source and drain regions,
a superlattice channel extending between the source and drain regions, the superlattice channel comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and
a gate comprising a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer;
wherein a superlattice is not located within the image processing circuitry.
17. The method of claim 16 wherein forming the first semiconductor chip further comprises forming an electrical interconnect layer beneath the array of image sensor pixels and defining a back side illumination (BSI) configuration therewith, the electrical interconnect layer electrically connecting the array of image sensor pixels with the readout circuitry.
18. The method of claim 16 further comprising positioning at least one lens overlying the array of image sensor pixels.
19. The method of claim 16 further comprising positioning at least one color filter overlying the array of image sensor pixels.
20. The method of claim 16 wherein the image processing circuitry also comprises a plurality of transistors each including a superlattice channel.