IP Library Granted Patent US 10,387,361
Granted Patent B2
US 10,387,361 · App. 15/846,122 · Granted Aug 20, 2019

Serial device with configuration mode for changing device behavior

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Quick Facts
Patent No.
US 10,387,361
App. No.
15/846,122
Granted
Aug 20, 2019
Kind
B2
Abstract

Systems, methods, circuits, devices and computer-readable mediums for configuring serial devices are disclosed. In some implementations, a device comprises: an input for receiving first and second requests from a serial bus; a decoder coupled to the input and configured to determine if either of the first and second requests is a configuration mode request; a controller coupled to the decoder and configured to: in response to a determination that the first request is a configuration mode request, program a configuration block with configuration data obtained from the serial bus and alter a device behavior according to the configuration data; and in response to a determination that the second request is not a configuration mode request, perform one or more actions on the device according to the second request.

Claims (54)

1. A device, comprising:

an input for receiving first and second requests from a serial bus;

a decoder coupled to the input and configured to determine if either of the first and second requests is a configuration mode request;

a controller coupled to the decoder and configured to:

in response to a determination that the first request is a configuration mode request, program a configuration block with configuration data obtained from the serial bus and alter a device behavior according to the configuration data; and

in response to a determination that the second request is not a configuration mode request, perform one or more actions on the device according to the second request.

2. The device of claim 1 , further comprising:

a memory array including the configuration block, and where, if the request is not a configuration request, the controller performs one or more memory operations on the memory array according to the request.

3. The device of claim 1 , where the configuration block is configured to report a device state to another device over the serial bus.

4. The device of claim 1 , where the serial bus is compliant with Inter-Integrated Circuit (I2C) bus protocol.

5. The device of claim 2 , where the configuration block further comprises:

a base configuration register for storing first configuration data for configuring the device; and one or more additional registers corresponding to one or more memory zones of the memory array, where the one or more additional registers store second configuration data that specify a write protection scheme of the corresponding one or more memory zones.

6. The device of claim 2 , further comprising:

a sensor coupled to a supply voltage and the controller, the sensor configured to sense an under voltage condition of the device based on configuration data in the configuration block.

7. The device of claim 2 , further comprising:

a write protection control module coupled to the controller, the write protection control configured to assert write protection on the memory array according to configuration data in the configuration block.

8. The device of claim 3 , where the device state indicates status of at least one of a memory access operation on the memory array, an error correcting operation and a count of error correction lifetime events with a monotonic counter.

9. A method of configuring a device, comprising:

receiving, by the device, first and second requests from a serial bus;

determining, by a decoder circuit, if either of the first and second requests is a configuration mode request;

in response to a determination that the first request is a configuration mode request:

programming, by the controller of the device, a configuration block with configuration data obtained from the serial bus and altering, by the controller of the device, device behavior according to the configuration data; and

in response to a determination that the second request is not a configuration mode request:

performing, by a controller of the device, one or more actions according to the second request.

10. The method of claim 9 , further comprising:

performing, by the controller of the device, one or more memory operations on a memory array of the device according to the request.

11. The method of claim 9 , where the configuration block is configured to report a device state to another device over the serial bus.

12. The method of claim 9 , where the serial bus is compliant with Inter-Integrated Circuit (I2C) bus protocol.

13. The method of claim 10 , further comprising:

storing first configuration data in a base register of the configuration block of the memory array for configuring the device and second configuration in one or more additional registers of the device corresponding to one or more memory zones of the memory array, the second configuration data specifying a write protection scheme for the one or more memory zones.

14. The method of claim 10 , further comprising:

determining, by a sensor of the device, an under voltage condition of the device; and

implementing, by the controller of the device, an under voltage lock out on the device using configuration data in the configuration block.

15. The method of claim 11 , where the device state indicates status of at least one of a memory access operation, error correcting operation and a count of error correction lifetime events.

16. The method of claim 10 , further comprising:

asserting, by a write protection control module of the device, write protection on the memory array according to configuration data in the configuration block.

17. A non-transitory, computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors of a device, causes the one or more processors of the device to perform operations comprising:

receiving, by the device, first and second requests from a serial bus;

determining, by a decoder circuit, if either of the first and second requests is a configuration mode request;

in response to a determination that the first request is a configuration mode request:

programming, by the controller of the device, a configuration block with configuration data obtained from the serial bus and altering, by the controller of the device, device behavior according to the configuration data; and

in response to a determination that the second request is not a configuration mode request:

performing, by a controller of the device, one or more actions according to the second request.

18. The non-transitory, computer-readable storage medium of claim 17 , the operations further comprising:

performing, by the controller of the device, one or more memory operations on a memory array of the device according to the request.

19. The non-transitory, computer-readable storage medium of claim 17 , where the configuration block is configured to report device state information to another device over the serial bus.

20. The non-transitory, computer-readable storage medium of claim 18 , the operations further comprising:

storing first configuration data in a base register of the configuration block of the memory array for configuring the device and second configuration in one or more additional registers of the device corresponding to one or more memory zones of the memory array, the second configuration data specifying a write protection scheme for the one or more memory zones.

21. The non-transitory, computer-readable storage medium of claim 18 , further comprising:

determining, by a sensor of the device, an under voltage condition of the device; and

implementing, by the one or more processors of the device, an under voltage lock out on the device using configuration data in the configuration block.

22. The non-transitory, computer-readable storage medium of claim 19 , where the device state indicates status of a memory access operation or error correcting operation.

23. The non-transitory, computer-readable storage medium of claim 18 , further comprising:

asserting, by a write protection control module of the device, write protection on the memory array according to configuration data in the configuration block.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2019
From: HARFERT, DANIEL; DE CARO, RICHARD V.
To: ATMEL CORPORATION
Reel/Frame 047896/0438 →