IP Library › Granted Patent US 10,622,428
Granted Patent B2
US 10,622,428 · App. 15/855,993 · Granted Apr 14, 2020

Backplane substrate, method of manufacturing the same, and organic light-emitting display device using the same

Inventors: Kum-Mi Oh (Seoul, KR); Shun-Young Yang (Bucheon-si, KR); Min-Seong Yun (Namyangju-si, KR)
Assignee: LG Display Co., Ltd.
H01L27/3262H01L27/124H01L27/127H01L27/1255H01L27/3211H01L27/3248H01L27/3276H01L29/66765H01L29/78678H01L27/1222H01L27/1262H01L27/3265H01L2227/323
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Quick Facts
Patent No.
US 10,622,428
App. No.
15/855,993
Granted
Apr 14, 2020
Kind
B2
Abstract

Disclosed are a backplane substrate that is capable of expressing high gradation even through a small pixel, a method of manufacturing the same, and an organic light-emitting display device using the same. Integration for ultra-high resolution is possible through structural modification.

Claims (37)

1. A backplane substrate comprising:

a substrate having a plurality of subpixels;

a driving thin-film transistor located at each subpixel and comprising a first gate electrode, a first active layer, a first source electrode and a first drain electrode connected to opposite sides of the first active layer, and a first gate insulating film disposed between the first active layer and the first gate electrode; and

a switching thin-film transistor electrically connected to the driving thin-film transistor at each subpixel and comprising a second gate electrode, a second active layer, a second source electrode and a second drain electrode connected to opposite sides of the second active layer, and a second gate insulating film disposed between the second active layer and the second gate electrode,

wherein the first active layer and the second active layer are located on a same layer,

the first gate electrode and the second gate electrode are located on different layers,

the first active layer has an offset area protruding from an edge of the first gate electrode by a predetermined width in a planar state and a first doped area is adjacent to the offset area, and the first gate electrode and the offset area do not overlap each other, and

wherein the first gate electrode overlaps the second active layer, and is connected to the second source electrode, and

wherein the second source electrode penetrates through the second active layer, and is connected to the first gate electrode in an overlapping region between the second active layer and the first gate electrode.

2. The backplane substrate according to claim 1 , wherein the second active layer has a second doped area vertically aligned with an edge of the second gate electrode.

3. The backplane substrate according to claim 1 , further comprising a first storage electrode that overlaps the first gate electrode.

4. The backplane substrate according to claim 3 , wherein the first storage electrode and the first gate electrode constitute a storage capacitor.

5. The backplane substrate according to claim 2 , wherein the first doped area and the second doped area are doped with a same dopant.

6. The backplane substrate according to claim 1 , further comprising a first gate auxiliary electrode that overlaps the offset area on a same layer as the second gate electrode.

7. The backplane substrate according to claim 1 , wherein the second source electrode, which is connected to the first gate electrode, has a planar portion on a layer different from a layer on which the second drain electrode is located.

8. The backplane substrate according to claim 7 , wherein the second source electrode is connected to the first gate electrode through a first contact hole between the planar portion of the second source electrode and the first gate electrode, and the second drain electrode is extended to the second active layer through a second contact hole.

9. The backplane substrate according to claim 8 , wherein the first contact hole has a larger depth than the second contact hole between an upper surface of the second drain electrode and the second active layer.

10. The backplane substrate according to claim 8 , further comprising a first storage auxiliary electrode that is connected to the first storage electrode and overlaps the planar portion of the second source electrode.

11. The backplane substrate according to claim 1 , wherein the first and second active layers are formed of polysilicon.

12. The backplane substrate according to claim 1 , wherein the first active layer has a first channel that overlaps the first gate electrode, and the second active layer has a second channel that overlaps the second gate electrode.

13. The backplane substrate according to claim 1 , wherein the offset area increases a period from an off state of the driving thin-film transistor.

14. The backplane substrate according to claim 1 , wherein the offset area increases a diversity of gradation.

15. The backplane substrate according to claim 1 , wherein the offset area is an intrinsic area.

16. The backplane substrate according to claim 1 , wherein the offset area and the first doped area do not overlap the first gate electrode.

17. The backplane substrate according to claim 1 , wherein the first active layer further includes a first undoped area adjacent to the offset area.

18. The backplane substrate according to claim 17 , wherein the offset area is disposed between the first undoped area and the first doped area, and the offset area is on the same layer as the first undoped area and the first doped area.

19. The backplane substrate according to claim 17 , wherein the first undoped area overlaps the first gate electrode.

20. An organic light-emitting display device having a backplane substrate comprising:

a substrate having a plurality of subpixels;

a driving thin-film transistor located at each subpixel and comprising a first gate electrode, a first active layer, a first source electrode and a first drain electrode connected to opposite sides of the first active layer, and a first gate insulating film disposed between the first active layer and the first gate electrode; and

a switching thin-film transistor electrically connected to the driving thin-film transistor at each subpixel and comprising a second gate electrode, a second active layer, a second source electrode and a second drain electrode connected to opposite sides of the second active layer, and a second gate insulating film disposed between the second active layer and the second gate electrode,

wherein the first active layer and the second active layer are located on a same layer,

the first gate electrode and the second gate electrode are located on different layers,

the first active layer has an offset area protruding from an edge of the first gate electrode by a predetermined width in a planar state, and a first doped area is adjacent to the offset area, and the first gate electrode and the offset area do not overlap each other, and

wherein the first gate electrode overlaps the second active layer, and is connected to the second source electrode, and

wherein the second source electrode penetrates through the second active layer, and is connected to the first gate electrode in an overlapping region between the second active layer and the first gate electrode; and

an organic light-emitting diode comprising a first electrode connected to the first source electrode, an organic emissive layer located on the first electrode, and a second electrode located on the organic emissive layer at each subpixel.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2018
From: OH, KUM-MI; YANG, SHUN-YOUNG; YUN, MIN-SEONG
To: LG DISPLAY CO., LTD.
Reel/Frame 044831/0078 →
Priority Claims (1)
KR 10-2016-0184420 · Dec 30, 2016 · national
Continuity (1)
Related Publication 20180190744A1 · Jul 5, 2018
Cited By (2)
US 12,349,540 US 12,477,782