Systems and methods to zero a tile register pair
Embodiments detailed herein relate to systems and methods to zero a tile register pair. In one example, a processor includes decode circuitry to decode a matrix pair zeroing instruction having fields for an opcode and an identifier to identify a destination matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded matrix pair zeroing instruction to zero every element of a left matrix and a right matrix of the identified destination matrix.
1. A processor comprising:
a matrix operations accelerator circuit comprising a two-dimensional grid of fused multiply accumulate circuits;
a first plurality of registers, that represents at least one two-dimensional destination matrix, coupled to the matrix operations accelerator circuit;
decode circuitry to decode a matrix pair zeroing instruction having fields to specify an opcode and the at least one two-dimensional destination matrix; and
execution circuitry to execute the decoded matrix pair zeroing instruction per the opcode to zero every element of a pair of destination matrices of the at least one two-dimensional destination matrix in response to a status register for the at least one two-dimensional destination matrix having a first field set to indicate the at least one two-dimensional destination matrix is valid and a second field set to indicate the at least one two-dimensional destination matrix comprises the pair of destination matrices.
2. The processor of claim 1 , wherein the opcode defines a size of each data element of the pair of destination matrices.
3. The processor of claim 2 , wherein the size of each data element of the pair of destination matrices is a doubleword.
4. The processor of claim 2 , wherein the size of each data element of the pair of destination matrices is a word.
5. The processor of claim 1 , wherein the execution circuitry is further to execute the decoded matrix pair zeroing instruction to zero any data elements in remaining columns and rows of the at least one two-dimensional destination matrix when zeroing the elements of the pair of destination matrices.
6. The processor of claim 1 , wherein the execution circuitry is to fault, for execution of the decoded matrix pair zeroing instruction, upon a determination that the second field is not set to indicate the at least one two-dimensional destination matrix comprises the pair of destination matrices.
7. A method comprising:
decoding, with decode circuitry of a hardware processor core coupled to a matrix operations accelerator circuit comprising a two-dimensional grid of fused multiply accumulate circuits, the matrix operations accelerator circuit coupled to a first plurality of registers that represents at least one two-dimensional destination matrix, a matrix pair zeroing instruction specifying an opcode and the at least one two-dimensional destination matrix; and
executing, with execution circuitry of the hardware processor core, the decoded matrix pair zeroing instruction per the opcode to zero every element of a pair of destination matrices of the at least one two-dimensional destination matrix in response to a status register for the at least one two-dimensional destination matrix having a first field set to indicate the at least one two-dimensional destination matrix is valid and a second field set to indicate the at least one two-dimensional destination matrix comprises the pair of destination matrices.
8. The method of claim 7 , wherein the opcode specifies a size of each data element of the pair of destination matrices.
9. The method of claim 8 , wherein the size of each data element of the pair of destination matrices is a doubleword.
10. The method of claim 8 , wherein the size of each data element of the pair of destination matrices is a word.
11. The method of claim 7 , wherein the executing the decoded matrix pair zeroing instruction further comprises zeroing any data elements in remaining columns and rows of the at least one two-dimensional destination matrix when zeroing the elements of the pair of destination matrices.
12. The method of claim 7 , wherein the executing the decoded matrix pair zeroing instruction further comprises faulting upon a determination that the second field is not set to indicate the at least one two-dimensional destination matrix comprises the pair of destination matrices.
13. A non-transitory machine-readable medium storing code that when executed by a machine causes the machine to perform a method comprising:
decoding, with decode circuitry of a hardware processor core coupled to a matrix operations accelerator circuit comprising a two-dimensional grid of fused multiply accumulate circuits, the matrix operations accelerator circuit coupled to a first plurality of registers that represents at least one two-dimensional destination matrix, a matrix pair zeroing instruction specifying an opcode and the at least one two-dimensional destination matrix; and
executing, with execution circuitry of the hardware processor core, the decoded matrix pair zeroing instruction per the opcode to zero every element of a pair of destination matrices of the at least one two-dimensional destination matrix in response to a status register for the at least one two-dimensional destination matrix having a first field set to indicate the at least one two-dimensional destination matrix is valid and a second field set to indicate the at least one two-dimensional destination matrix comprises the pair of destination matrices.
14. The non-transitory machine-readable medium of claim 13 , wherein the opcode defines a size of each data element of the pair of destination matrices.
15. The non-transitory machine-readable medium of claim 13 , wherein the executing the decoded matrix pair zeroing instruction further comprises zeroing any data elements in remaining columns and rows of the at least one two-dimensional destination matrix when zeroing the elements of the pair of destination matrices.
16. The processor of claim 1 , wherein the execution circuitry is to operate on one row of the at least one two-dimensional destination matrix at a time, starting with a first row.
17. The processor of claim 1 , wherein the execution circuitry is to operate on one chunk of C bytes at a time of a row being operated on, C being a positive integer ranging between 1 byte and a whole row of bytes.
18. The method of claim 7 , wherein the executing is performed in parallel on one row of elements of the at least one two-dimensional destination matrix at a time, starting with a first row.
19. The method of claim 7 , wherein the executing is performed in parallel on one chunk of C bytes at a time of a row being operated on, C being a positive integer ranging between 1 byte and a whole row of bytes.
20. The processor of claim 6 , wherein the execution circuitry is to fault, for execution of the decoded matrix pair zeroing instruction, upon a determination that the first field is not set to indicate the at least one two-dimensional destination matrix is valid.
21. The method of claim 12 , wherein the executing the decoded matrix pair zeroing instruction further comprises faulting upon a determination that the first field is not set to indicate the at least one two-dimensional destination matrix is valid.
22. The non-transitory machine-readable medium of claim 13 , wherein the executing the decoded matrix pair zeroing instruction further comprises faulting upon a determination that the second field is not set to indicate the at least one two-dimensional destination matrix comprises the pair of destination matrices.
23. A system comprising:
a matrix operations accelerator circuit comprising:
a two-dimensional grid of fused multiply accumulate circuits, and
a first plurality of registers, that represents at least one two-dimensional destination matrix, coupled to the two-dimensional grid of fused multiply accumulate circuits; and
a hardware processor coupled to the matrix operations accelerator circuit, the hardware processor comprising:
decode circuitry to decode a matrix pair zeroing instruction having fields to specify an opcode and the at least one two-dimensional destination matrix, and
execution circuitry to execute the decoded matrix pair zeroing instruction per the opcode to zero every element of a pair of destination matrices of the at least one two-dimensional destination matrix in response to a status register for the at least one two-dimensional destination matrix having a first field set to indicate the at least one two-dimensional destination matrix is valid and a second field set to indicate the at least one two-dimensional destination matrix comprises the pair of destination matrices.
24. The system of claim 23 , wherein the execution circuitry is to operate on one row of the at least one two-dimensional destination matrix at a time, starting with a first row.
25. The system of claim 23 , wherein the execution circuitry is to operate on one chunk of C bytes at a time of a row being operated on, C being a positive integer ranging between 1 byte and a whole row of bytes.