Circuits based on complementary field-effect transistors

1. A structure comprising:

a trench isolation having a top surface;

a first complementary field-effect transistor including a first nanosheet transistor with a source/drain region and a second nanosheet transistor having a source/drain region, the source/drain region of the second nanosheet transistor stacked over the source/drain region of the first nanosheet transistor;

a second complementary field-effect transistor including a first nanosheet transistor with a functional gate structure that is coupled with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor; and

a contact extending vertically to connect the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor,

wherein the functional gate structure of the first nanosheet transistor of the second complementary field-effect transistor and the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor are arranged on the top surface of the trench isolation.

2. The structure of claim 1 further comprising:

a buried interconnect on the top surface of the trench isolation, the buried interconnect coupling the functional gate structure of the nanosheet transistor of the second complementary field-effect transistor with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor.

3. The structure of claim 2 further comprising:

a dielectric layer arranged between the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor,

wherein the buried interconnect is arranged between the top surface of the trench isolation and the dielectric layer.

4. The structure of claim 1 further comprising:

a buried interconnect beneath the top surface of the trench isolation,

wherein the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor is arranged on the top surface of the trench isolation, and the buried interconnect is coupled with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor.

5. The structure of claim 4 wherein the buried interconnect couples a positive supply voltage line or a ground line with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor.

6. The structure of claim 1 wherein the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor has a first side edge, the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor has a second side edge, and the contact is connected with the first side edge and the second side edge.

7. The structure of claim 1 further comprising:

an access nanosheet transistor having a first source/drain region and a first nanosheet channel layer coupling the first source/drain region of the access nanosheet transistor with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor.

8. The structure of claim 7 further comprising:

a dielectric layer arranged between the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor,

wherein the first nanosheet channel layer and the first source/drain region of the access nanosheet transistor are arranged below the dielectric layer, the access nanosheet transistor includes a second nanosheet channel layer that is arranged above the dielectric layer, and the access nanosheet transistor lacks a second source/drain region above the dielectric layer.

9. A structure comprising:

a trench isolation having a top surface;

a first complementary field-effect transistor including a first nanosheet transistor with a source/drain region, and a second nanosheet transistor having a source/drain region, the source/drain region of the second nanosheet transistor stacked over the source/drain region of the first nanosheet transistor; and

a second complementary field-effect transistor including a first nanosheet transistor with a functional gate structure that is coupled with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor,

wherein the functional gate structure of the nanosheet transistor of the second complementary field-effect transistor and the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor are arranged on the top surface of the trench isolation.

10. The structure of claim 9 further comprising:

a buried interconnect on the top surface of the trench isolation, the buried interconnect coupling the functional gate structure of the nanosheet transistor of the second complementary field-effect transistor with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor.

11. The structure of claim 10 further comprising:

a dielectric layer arranged between the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor,

wherein the buried interconnect is arranged between the top surface of the trench isolation and the dielectric layer.

12. The structure of claim 9 wherein the first complementary field-effect transistor includes a functional gate structure, and the first nanosheet transistor of the second complementary field-effect transistor includes a source/drain region that is coupled with the functional gate structure of the first complementary field-effect transistor.

13. The structure of claim 12 wherein the second complementary field-effect transistor includes a second nanosheet transistor having a source/drain region, and the source/drain region of the second nanosheet transistor of the second complementary field-effect transistor is stacked over the source/drain region of the first nanosheet transistor of the second complementary field-effect transistor.

14. The structure of claim 9 further comprising:

a dielectric layer arranged between the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor.

15. The structure of claim 9 further comprising:

a first access nanosheet transistor having a source/drain region and a nanosheet channel layer coupling the source/drain region of the access nanosheet transistor with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor.

16. The structure of claim 15 wherein the first complementary field-effect transistor includes a functional gate structure, and the first nanosheet transistor of the second complementary field-effect transistor includes a source/drain region that is coupled with the functional gate structure of the first complementary field-effect transistor, and further comprising:

a second access nanosheet transistor having a source/drain region and a nanosheet channel layer coupling the source/drain region of the second access nanosheet transistor with the source/drain region of the first nanosheet transistor of the second complementary field-effect transistor.

17. A method comprising:

forming a trench isolation having a top surface;

forming a first complementary field-effect transistor including a first nanosheet transistor with a source/drain region and a second nanosheet transistor having a source/drain region, wherein the source/drain region of the second nanosheet transistor is stacked over the source/drain region of the first nanosheet transistor;

forming a second complementary field-effect transistor including a nanosheet transistor with a functional gate structure that is coupled with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor; and

forming a contact extending vertically to connect the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor

wherein the functional gate structure of the nanosheet transistor of the second complementary field-effect transistor and the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor are arranged on the top surface of the trench isolation.

18. The method of claim 17 wherein the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor has a first side edge, the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor has a second side edge, and the contact is connected with the first side edge and the second side edge.

19. The method of claim 17 further comprising:

forming a buried interconnect on the top surface of the trench isolation,

wherein the buried interconnect couples the functional gate structure of the nanosheet transistor of the second complementary field-effect transistor with the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor.

20. The method of claim 19 further comprising:

forming a dielectric layer that is arranged between the source/drain region of the first nanosheet transistor of the first complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the first complementary field-effect transistor,

wherein the buried interconnect is arranged between the top surface of the trench isolation and the dielectric layer.