Transistors with dual power and signal lines
A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.
1. A semiconductor structure, comprising:
a first field-effect transistor comprising:
a first back side source/drain contact;
a second back side source/drain contact;
a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively;
a back-end-of-line layer on a back side of the first field-effect transistor; and
a second power line connected to the back-end-of-line layer on the back side of the first field-effect transistor; and
a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising:
a first front side source/drain contact;
a second front side source/drain contact;
a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively;
a back-end-of-line layer on a front side of the second field-effect transistor; and
a second power line connected to the back-end-of-line layer on the front side of the second field-effect transistor; and
the second power line of the first field-effect transistor being connected to the second power line of the second field-effect transistor by a first interconnect structure.
2. The semiconductor structure of claim 1 , wherein:
the first field-effect transistor further comprises a first source/drain region disposed on the first back side source/drain contact and a second source/drain region disposed on the second back side source/drain contact;
the second field-effect transistor further comprises a first source/drain region disposed on the first front side source/drain contact and a second source/drain region disposed on the second front side source/drain contact;
the first source/drain region of the second field-effect transistor being stacked above the first source/drain region of the first field-effect transistor; and
the second source/drain region of the second field-effect transistor being stacked above the second source/drain region of the first field-effect transistor.
3. The semiconductor structure of claim 2 , wherein:
the first field-effect transistor further comprises a third source/drain region;
the second field-effect transistor further comprises a third source/drain region; and
the third source/drain region of the second field-effect transistor is stacked above the third source/drain region of the first field-effect transistor.
4. The semiconductor structure of claim 3 , further comprising a metal contact disposed on each of the third source/drain region of the second field-effect transistor and the third source/drain region of the first field-effect transistor.
5. The semiconductor structure of claim 1 , wherein the first power line and the first signal line of the first field-effect transistor are disposed within a first dielectric layer.
6. The semiconductor structure of claim 5 , wherein the first power line and the first signal line of the second field-effect transistor are disposed within a second dielectric layer.
7. The semiconductor structure of claim 1 , wherein:
the first field-effect transistor further comprises a second signal line connected to the back-end-of-line layer on the back side;
the second field-effect transistor further comprises a second signal line connected to the back-end-of-line layer on the front side; and
the second signal line of the first field-effect transistor being connected to the second signal line of the second field-effect transistor by a second interconnect structure.
8. The semiconductor structure of claim 1 , wherein the first field-effect transistor and the second field-effect transistor comprise respective nanosheet field-effect transistor devices.
9. An integrated circuit, comprising:
one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
a first field-effect transistor comprising:
a first back side source/drain contact;
a second back side source/drain contact;
a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively;
a back-end-of-line layer on a back side of the first field-effect transistor; and
a second power line connected to the back-end-of-line layer on the back side of the first field-effect transistor; and
a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising:
a first front side source/drain contact;
a second front side source/drain contact;
a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively
a back-end-of-line layer on a front side of the second field-effect transistor; and
a second power line connected to the back-end-of-line layer on the front side of the second field-effect transistor; and
the second power line of the first field-effect transistor being connected to the second power line of the second field-effect transistor by a first interconnect structure.
10. The integrated circuit of claim 9 , wherein:
the first field-effect transistor further comprises a first source/drain region disposed on the first back side source/drain contact and a second source/drain region disposed on the second back side source/drain contact;
the second field-effect transistor further comprises a first source/drain region disposed on the first front side source/drain contact and a second source/drain region disposed on the second front side source/drain contact;
the first source/drain region of the second field-effect transistor being stacked above the first source/drain region of the first field-effect transistor; and
the second source/drain region of the second field-effect transistor being stacked above the second source/drain region of the first field-effect transistor.
11. The integrated circuit of claim 10 , wherein:
the first field-effect transistor further comprises a third source/drain region;
the second field-effect transistor further comprises a third source/drain region; and
the third source/drain region of the second field-effect transistor is stacked above the third source/drain region of the first field-effect transistor.
12. The integrated circuit of claim 11 , further comprising a metal contact disposed on each of the third source/drain region of the second field-effect transistor and the third source/drain region of the first field-effect transistor.
13. The integrated circuit of claim 9 , wherein the first power line and the first signal line of the first field-effect transistor are disposed within a first dielectric layer.
14. The integrated circuit of claim 13 , wherein the first power line and the first signal line of the second field-effect transistor are disposed within a second dielectric layer.
15. The integrated circuit of claim 9 , wherein:
the first field-effect transistor further comprises a second signal line connected to the back-end-of-line layer on the back side;
the second field-effect transistor further comprises a second signal line connected to the back-end-of-line layer on the front side; and
the second signal line of the first field-effect transistor being connected to the second signal line of the second field-effect transistor by a second interconnect structure.
16. The integrated circuit of claim 9 , wherein the first field-effect transistor and the second field-effect transistor comprise respective nanosheet field-effect transistor devices.
17. A method, comprising:
forming a first field-effect transistor comprising a first back side source/drain contact; a second back side source/drain contact; a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively;
forming a back-end-of-line layer on a back side of the first field-effect transistor; and a second power line connected to the back-end-of-line layer on the back side of the first field-effect transistor; and
forming a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising a first front side source/drain contact; a second front side source/drain contact; a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively;
forming a back-end-of-line layer on a front side of the second field-effect transistor; and a second power line connected to the back-end-of-line layer on the front side of the second field-effect transistor; and
connecting the second power line of the first field-effect transistor to the second power line of the second field-effect transistor by a first interconnect structure.
18. The method of claim 17 , further comprising:
forming a second signal line connected to the back-end-of-line layer on the back side of the first field-effect transistor;
forming a second signal line connected to the back-end-of-line layer on the front side of the second field-effect transistor; and
forming a second interconnect structure connecting the second signal line of the first field-effect transistor to the second signal line of the second field-effect transistor.
19. The method of claim 17 , further comprising:
forming a first source/drain region disposed on the first back side source/drain contact of the first field-effect transistor and a second source/drain region disposed on the second back side source/drain contact of the first field-effect transistor;
forming a first source/drain region disposed on the first front side source/drain contact of the second field-effect transistor and a second source/drain region disposed on the second front side source/drain contact of the second field-effect transistor.
20. The method of claim 19 , wherein:
the first source/drain region of the second field-effect transistor is stacked above the first source/drain region of the first field-effect transistor; and
the second source/drain region of the second field-effect transistor is stacked above the second source/drain region of the first field-effect transistor.