Semiconductor wafer and method of ball drop on thin wafer with edge support ring
A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.
1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer;
forming a conductive layer over a surface of the semiconductor wafer;
providing a first stencil including a plurality of first openings; and
disposing the first stencil over the edge support ring with the first openings extending below a top surface of the edge support ring to contact the conductive layer;
wherein the first stencil is unitary.
2. The method of claim 1 , further including dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer.
3. The method of claim 2 , further including:
bonding the bumps to the conductive layer; and
removing the first stencil.
4. The method of claim 1 , wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil.
5. The method of claim 1 , further including:
providing a second stencil including a plurality of second openings;
disposing a second stencil over the edge support ring with the second openings extending to and aligned with the conductive layer; and
depositing a flux material in the second openings over the conductive layer.
6. The method of claim 1 , wherein the first stencil includes a notch disposed over the edge support ring.
7. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a conductive layer formed over a surface of the semiconductor wafer and an edge support ring around a perimeter of the semiconductor wafer;
providing a first stencil including a plurality of first openings; and
disposing the first stencil over the edge support ring with the first openings aligned with and extending to the conductive layer;
wherein the first stencil is unitary.
8. The method of claim 7 , further including dispersing a plurality of bumps over the first stencil to occupy the first openings over the conductive layer.
9. The method of claim 8 , further including:
bonding the bumps to the conductive layer; and
removing the first stencil.
10. The method of claim 7 , wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil.
11. The method of claim 7 , further including:
providing a second stencil including a plurality of second openings;
disposing a second stencil over the edge support ring with the second openings extending to and aligned with the conductive layer; and
depositing a flux material in the second openings over the conductive layer.
12. The method of claim 7 , wherein the first stencil includes a notch disposed over the edge support ring.
13. The method of claim 7 , wherein the first stencil includes a horizontal portion and a step-down portion extending from a top surface of the edge support ring to the horizontal portion of the first stencil.
14. A semiconductor wafer, comprising:
a semiconductor wafer including an edge support ring around a perimeter of the semiconductor wafer and a conductive layer formed over a surface of the semiconductor wafer; and
a first stencil including a plurality of first openings, wherein the first stencil is disposed over the edge support ring with the first openings extending below a top surface of the edge support ring to the conductive layer;
wherein the first stencil is unitary.
15. The semiconductor wafer of claim 14 , further including a plurality of bumps disposed over the first stencil to occupy the first openings over the conductive layer.
16. The semiconductor wafer of claim 14 , wherein the first stencil includes a horizontal portion containing the first openings and a vertical extension disposed over the edge support ring and extending to the horizontal portion of the first stencil.
17. The semiconductor wafer of claim 14 , further including:
a second stencil including a plurality of second openings, wherein the second stencil is disposed over the edge support ring with the second openings extending to and aligned with the conductive layer; and
a flux material deposited in the second openings over the conductive layer.
18. The semiconductor wafer of claim 17 , wherein the second stencil includes a horizontal portion and a sloped portion extending from a top surface of the edge support ring to the horizontal portion of the second stencil.
19. The semiconductor wafer of claim 14 , wherein the first stencil includes a notch disposed over the edge support ring.
20. The semiconductor wafer of claim 14 , wherein the first stencil includes a horizontal portion and a step-down portion extending from a top surface of the edge support ring to the horizontal portion of the first stencil.