Semiconductor device, and display device and electronic device utilizing the same
A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101 , the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.
1. A display device comprising:
pixels;
the gate line driver circuit; and
a signal line driver circuit;
wherein the pixels and the gate line driver circuit are provided over a substrate,
wherein at least part of the signal line driver circuit is provided with an IC chip,
wherein the IC chip comprises a single crystal substrate or an SOI substrate,
wherein the gate line driver circuit is electrically connected to the pixels,
wherein the signal line driver circuit is electrically connected to the pixels,
wherein the gate line driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, and
wherein:
one of a source and a drain of the first transistor is electrically connected to a first wiring;
the other of the source and the drain of the first transistor is electrically connected to a second wiring;
one of a source and a drain of the second transistor is electrically connected to a third wiring;
the other of the source and the drain of the second transistor is electrically connected to the second wiring;
a gate of the second transistor is electrically connected to a fourth wiring;
one of a source and a drain of the third transistor is electrically connected to a fifth wiring;
the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor;
a gate of the third transistor is electrically connected to the fifth wiring;
one of a source and a drain of the fourth transistor is electrically connected to the third wiring;
the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fourth transistor;
one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the fourth transistor;
the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor; and
a gate of the fifth transistor is electrically connected to the fourth wiring.
2. The display device according to claim 1 , wherein the IC chip is connected to the substrate by COG.
3. The display device according to claim 1 , wherein the IC chip is connected to the substrate by TAB.
4. The display device according to claim 1 ;
the one of the source and the drain of the first transistor is directly connected to the first wiring;
the other of the source and the drain of the first transistor is directly connected to the second wiring;
the one of the source and the drain of the second transistor is directly connected to the third wiring;
the other of the source and the drain of the second transistor is directly connected to the second wiring;
the gate of the second transistor is directly connected to the fourth wiring;
the one of the source and the drain of the third transistor is directly connected to the fifth wiring;
the gate of the third transistor is directly connected to the fifth wiring;
the one of the source and the drain of the fourth transistor is directly connected to the third wiring;
the other of the source and the drain of the fourth transistor is directly connected to the fourth transistor;
the one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor;
the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor; and
the gate of the fifth transistor is directly connected to the fourth wiring.
5. The display device according to claim 1 ;
wherein the gate line driver circuit further comprises a sixth transistor and a seventh transistor, and
wherein:
a gate of the sixth transistor is electrically connected to the gate of the first transistor;
one of a source and a drain of the sixth transistor is electrically connected to a sixth wiring;
a gate of the seventh transistor is electrically connected to the fourth wiring; and
one of a source and a drain of the seventh transistor is electrically connected to the sixth wiring.
6. The semiconductor device according to claim 5 , wherein:
the one of the source and the drain of the first transistor is directly connected to a first wiring;
the other of the source and the drain of the first transistor is directly connected to a second wiring;
the one of the source and the drain of the second transistor is directly connected to a third wiring;
the other of the source and the drain of the second transistor is directly connected to the second wiring;
the gate of the second transistor is directly connected to a fourth wiring;
the one of the source and the drain of the third transistor is directly connected to the fifth wiring;
the gate of the third transistor is directly connected to the fifth wiring;
the one of the source and the drain of the fourth transistor is directly connected to the third wiring;
the other of the source and the drain of the fourth transistor is directly connected to the fourth transistor;
the one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor;
the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor;
the gate of the fifth transistor is directly connected to the fourth wiring;
the gate of the sixth transistor is directly connected to the gate of the first transistor;
the one of the source and the drain of the sixth transistor is directly connected to a sixth wiring;
the gate of the seventh transistor is directly connected to the fourth wiring; and
the one of the source and the drain of the seventh transistor is directly connected to the sixth wiring.
7. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor; and
a fifth transistor;
wherein:
one of a source and a drain of the first transistor is electrically connected to a first wiring;
the other of the source and the drain of the first transistor is electrically connected to a second wiring;
one of a source and a drain of the second transistor is electrically connected to a third wiring;
the other of the source and the drain of the second transistor is electrically connected to the second wiring;
a gate of the second transistor is electrically connected to a fourth wiring;
one of a source and a drain of the third transistor is electrically connected to a fifth wiring;
the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor;
a gate of the third transistor is electrically connected to the fifth wiring;
one of a source and a drain of the fourth transistor is electrically connected to the third wiring;
the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fourth transistor;
one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the fourth transistor;
the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor; and
a gate of the fifth transistor is electrically connected to the fourth wiring.
8. The semiconductor device according to claim 7 , wherein:
the one of the source and the drain of the first transistor is directly connected to the first wiring;
the other of the source and the drain of the first transistor is directly connected to the second wiring;
the one of the source and the drain of the second transistor is directly connected to the third wiring;
the other of the source and the drain of the second transistor is directly connected to the second wiring;
the gate of the second transistor is directly connected to the fourth wiring;
the one of the source and the drain of the third transistor is directly connected to the fifth wiring;
the gate of the third transistor is directly connected to the fifth wiring;
the one of the source and the drain of the fourth transistor is directly connected to the third wiring;
the other of the source and the drain of the fourth transistor is directly connected to the fourth transistor;
the one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor;
the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor; and
the gate of the fifth transistor is directly connected to the fourth wiring.
9. The semiconductor device according to claim 7 , further comprising a sixth transistor and a seventh transistor,
wherein:
a gate of the sixth transistor is electrically connected to the gate of the first transistor;
one of a source and a drain of the sixth transistor is electrically connected to a sixth wiring;
a gate of the seventh transistor is electrically connected to the fourth wiring; and
one of a source and a drain of the seventh transistor is electrically connected to the sixth wiring.
10. The semiconductor device according to claim 9 , wherein:
the one of the source and the drain of the first transistor is directly connected to the first wiring;
the other of the source and the drain of the first transistor is directly connected to the second wiring;
the one of the source and the drain of the second transistor is directly connected to the third wiring;
the other of the source and the drain of the second transistor is directly connected to the second wiring;
the gate of the second transistor is directly connected to the fourth wiring;
the one of the source and the drain of the third transistor is directly connected to the fifth wiring;
the gate of the third transistor is directly connected to the fifth wiring;
the one of the source and the drain of the fourth transistor is directly connected to the third wiring;
the other of the source and the drain of the fourth transistor is directly connected to the fourth transistor;
the one of the source and the drain of the fifth transistor is directly connected to the other of the source and the drain of the fourth transistor;
the other of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor;
the gate of the fifth transistor is directly connected to the fourth wiring;
the gate of the sixth transistor is directly connected to the gate of the first transistor;
the one of the source and the drain of the sixth transistor is directly connected to the sixth wiring;
the gate of the seventh transistor is directly connected to the fourth wiring; and
the one of the source and the drain of the seventh transistor is directly connected to the sixth wiring.