Granted Patent B2

US 12,652,049 · App. 18/766,726 · Granted Jun 9, 2026

Inventors: Hiroki Inoue (Atsugi, JP); Munehiro Kozuma (Atsugi, JP); Takeshi Aoki (Ebina, JP); Shuji Fukai (Atsugi, JP); Fumika Akasawa (Sagamihara, JP); Shintaro Harada (Kawasaki, JP); Sho Nagao (Atsugi, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H03K19/094H10D84/811

Abstract

Claims (31)

1 . A semiconductor device comprising:

first to seventh transistors;

first to third capacitors;

first and second wirings;

first to fourth input terminals; and

an output terminal,

wherein one of a source and a drain of the sixth transistor and one of a source and a drain of the seventh transistor are electrically connected to the first wiring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the seventh transistor, one of a source and a drain of the third transistor, one terminal of the third capacitor, and a gate of the fifth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring,

wherein a gate of the sixth transistor is electrically connected to the first input terminal, one terminal of the first capacitor, and a gate of the first transistor,

wherein a gate of the seventh transistor is electrically connected to the second input terminal, one terminal of the second capacitor, and a gate of the second transistor,

wherein a gate of the third transistor is electrically connected to the third input terminal,

wherein a gate of the fourth transistor is electrically connected to the fourth input terminal,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to the first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor, the other terminal of the first capacitor, the other terminal of the second capacitor, the other terminal of the third capacitor, one of a source and a drain of the fifth transistor, and the output terminal, and

wherein the other of the source and the drain of the fifth transistor is electrically connected to the second wiring.

2 . The semiconductor device according to claim 1 ,

wherein a first potential is supplied to the first wiring,

wherein a second potential is supplied to the second wiring,

wherein the second potential is a potential higher than the first potential,

wherein a first signal is input to the first input terminal,

wherein a second signal is input to the second input terminal,

wherein a third signal is input to the third input terminal,

wherein a fourth signal is input to the fourth input terminal,

wherein the third signal is a signal with an inverted logic of the first signal, and

wherein the fourth signal is a signal with an inverted logic of the second signal.

3 . The semiconductor device according to claim 1 ,

wherein the first to seventh transistors are each an n-channel transistor.

4 . The semiconductor device according to claim 1 ,

wherein the first to seventh transistors each comprise a metal oxide in a channel formation region.

Priority Claims (1)

Continuity (2)

References Cited (169)