IP Library › Granted Patent US 12,490,518
Granted Patent B2
US 12,490,518 · App. 18/383,078 · Granted Dec 2, 2025

Semiconductor device and display device

Inventors: Hajime Kimura (Kanagawa, JP); Atsushi Umezaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D86/60G02F1/13306G02F1/1339G02F1/136213G02F1/136286G02F1/1368G11C19/28H10D30/6729H10D30/673H10D30/6755H10D30/6757H10D84/83H10D86/0221H10D86/0231H10D86/423H10D86/441H10D86/443H10D86/471H10D86/481G02F1/133302G02F1/133345G02F1/134309G02F2201/121G02F2201/123G09G3/3677G09G2310/0251G09G2310/08G09G2330/021
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Quick Facts
Patent No.
US 12,490,518
App. No.
18/383,078
Granted
Dec 2, 2025
Kind
B2
Abstract

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

Claims (111)

1 . A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a second wiring,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a third wiring,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second wiring,

wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a fourth wiring,

wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a fifth wiring,

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor,

wherein a gate electrode of the fourth transistor is electrically connected to a sixth wiring,

wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to the fifth wiring,

wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor,

wherein a gate electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor,

wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to the fourth wiring,

wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to a gate electrode of the third transistor,

wherein a gate electrode of the sixth transistor is electrically connected to the fourth wiring,

wherein one of a source electrode and a drain electrode of the seventh transistor is electrically connected to the fifth wiring,

wherein the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the gate electrode of the third transistor, and

wherein a gate electrode of the seventh transistor is electrically connected to the sixth wiring.

2 . The semiconductor device according to claim 1 , further comprising an eighth transistor,

wherein the gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the eighth transistor.

3 . The semiconductor device according to claim 1 , wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are n-channel transistors.

4 . The semiconductor device according to claim 1 , wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are p-channel transistors.

5 . The semiconductor device according to claim 1 ,

wherein an input signal is input to the gate electrode of the first transistor,

wherein a first signal is input to the fourth wiring,

wherein a second signal is input to the sixth wiring,

wherein the first signal is different from the second signal, and

wherein an output signal is output to the second wiring.

6 . A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a second wiring,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a third wiring,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second wiring,

wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a fourth wiring,

wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a fifth wiring,

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor,

wherein a gate electrode of the fourth transistor is electrically connected to a sixth wiring,

wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to the fifth wiring,

wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor,

wherein a gate electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor,

wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to the fourth wiring,

wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to a gate electrode of the third transistor,

wherein a gate electrode of the sixth transistor is electrically connected to the fourth wiring,

wherein one of a source electrode and a drain electrode of the seventh transistor is electrically connected to the fifth wiring,

wherein the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the gate electrode of the third transistor,

wherein a gate electrode of the seventh transistor is electrically connected to the sixth wiring,

wherein an input signal is input to the gate electrode of the first transistor,

wherein a first signal is input to the fourth wiring,

wherein a second signal is input to the sixth wiring,

wherein the first signal is different from the second signal,

wherein an output signal is output to the second wiring, and

wherein an area where the other of the source electrode and the drain electrode of the third transistor overlaps with the gate electrode of the third transistor is larger than an area where the one of the source electrode and the drain electrode of the third transistor overlaps with the gate electrode of the third transistor.

7 . The semiconductor device according to claim 6 , further comprising an eighth transistor,

wherein the gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the eighth transistor.

8 . The semiconductor device according to claim 6 , wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are n-channel transistors.

9 . The semiconductor device according to claim 6 , wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are p-channel transistors.

10 . The semiconductor device according to claim 6 ,

wherein an input signal is input to the gate electrode of the first transistor,

wherein a first signal is input to the fourth wiring,

wherein a second signal is input to the sixth wiring,

wherein the first signal is different from the second signal, and

wherein an output signal is output to the second wiring.

11 . A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a second wiring,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a third wiring,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second wiring,

wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a fourth wiring,

wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a fifth wiring,

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor,

wherein a gate electrode of the fourth transistor is electrically connected to a sixth wiring,

wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to the fifth wiring,

wherein the other of the source electrode and the drain electrode of the fifth transistor is electrically connected to the gate electrode of the second transistor,

wherein a gate electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor,

wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to the fourth wiring,

wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to a gate electrode of the third transistor,

wherein a gate electrode of the sixth transistor is electrically connected to the fourth wiring,

wherein one of a source electrode and a drain electrode of the seventh transistor is electrically connected to the fifth wiring,

wherein the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the gate electrode of the third transistor,

wherein a gate electrode of the seventh transistor is electrically connected to the sixth wiring,

wherein an input signal is input to the gate electrode of the first transistor,

wherein an output signal is output to the second wiring, and

wherein an area where the other of the source electrode and the drain electrode of the third transistor overlaps with the gate electrode of the third transistor is larger than an area where the one of the source electrode and the drain electrode of the third transistor overlaps with the gate electrode of the third transistor.

12 . The semiconductor device according to claim 11 , further comprising an eighth transistor,

wherein the gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the eighth transistor.

13 . The semiconductor device according to claim 11 , wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are n-channel transistors.

14 . The semiconductor device according to claim 11 , wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are p-channel transistors.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2023
From: KIMURA, HAJIME; UMEZAKI, ATSUSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 065318/0887 →
Priority Claims (1)
JP 2009-209099 · Sep 10, 2009 · national
Continuity (8)
Continuation 16878755 · May 20, 2020
Continuation 16275385 · Feb 14, 2019
Continuation 15810228 · Nov 13, 2017
Continuation 15334397 · Oct 26, 2016
Continuation 15231851 · Aug 9, 2016
Continuation 14658403 · Mar 16, 2015
Continuation 12875808 · Sep 3, 2010
Related Publication 20240145485A1 · May 2, 2024
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