IP Library Granted Patent US 10,269,609
Granted Patent B2
US 10,269,609 · App. 15/883,625 · Granted Apr 23, 2019

Wafer level flat no-lead semiconductor packages and methods of manufacture

Inventors: Darrell D. Truhitte (Phoenix, AZ); James P. Letterman, Jr. (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/6835H01L21/4832H01L21/561H01L21/6836H01L23/3107H01L24/11H01L24/27H01L24/49H01L24/92H01L24/94H01L24/95H01L24/96H01L24/97H01L21/568H01L21/78H01L23/3114H01L23/36H01L23/49537H01L24/13H01L24/16H01L24/29H01L24/32H01L24/33H01L24/48H01L24/75H01L24/81H01L24/83H01L24/85H01L25/0657H01L25/105H01L2221/68304H01L2221/68327H01L2221/68377H01L2221/68381H01L2224/04105H01L2224/11H01L2224/11003H01L2224/116H01L2224/119H01L2224/1132H01L2224/1146H01L2224/11312H01L2224/11334H01L2224/11418H01L2224/11462H01L2224/131H01L2224/1308H01L2224/1319H01L2224/13124H01L2224/13139H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/13164H01L2224/13166H01L2224/16245H01L2224/16258H01L2224/27003H01L2224/276H01L2224/279H01L2224/2732H01L2224/2746H01L2224/27312H01L2224/27334H01L2224/27418H01L2224/27462H01L2224/291H01L2224/2908H01L2224/2919H01L2224/29124H01L2224/29139H01L2224/29144H01L2224/29147H01L2224/29155H01L2224/29164H01L2224/29166H01L2224/32245H01L2224/32258H01L2224/33181H01L2224/45015H01L2224/4811H01L2224/48091H01L2224/48111H01L2224/48145H01L2224/48247H01L2224/48465H01L2224/49109H01L2224/73204H01L2224/73265H01L2224/753H01L2224/75251H01L2224/75252H01L2224/75755H01L2224/75756H01L2224/8121H01L2224/81192H01L2224/81805H01L2224/81815H01L2224/81856H01L2224/83H01L2224/83005H01L2224/8321H01L2224/83191H01L2224/83192H01L2224/83805H01L2224/83815H01L2224/83856H01L2224/85005H01L2224/92H01L2224/92125H01L2224/92147H01L2224/92227H01L2224/94H01L2224/95H01L2224/97H01L2924/00014H01L2924/181H01L2924/3511
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Quick Facts
Patent No.
US 10,269,609
App. No.
15/883,625
Granted
Apr 23, 2019
Kind
B2
Abstract

Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

Claims (29)

1. A method of manufacturing a semiconductor package, the method comprising:

providing a first base frame;

applying die attach material on the first base frame;

bonding a wafer comprising a plurality of semiconductor die to the first base frame at one or more die pads comprised in each one of the plurality of semiconductor die through the die attach material;

singulating the plurality of semiconductor die;

applying die attach material to one of the plurality of semiconductor die and a second base frame;

bonding the second base frame to the plurality of semiconductor die through the die attach material;

one of overmolding or underfilling the plurality of semiconductor die between the first base frame and the second base frame; and

singulating the first and second base frames to form a plurality of semiconductor packages.

2. The method of claim 1 , wherein the semiconductor package is a press fit package.

3. The method of claim 1 , wherein the first base frame comprises a plurality of terminals.

4. The method of claim 1 , wherein the second base frame comprises a plurality of terminals.

5. The method of claim 1 , wherein an epoxy based resin is used in the one of overmolding or underfilling the plurality of semiconductor die between the first base frame and the second base frame.

6. The method of claim 1 , wherein both overmolding and underfilling are used to encapsulate the die.

7. The method of claim 1 , wherein the die attach film comprises solder.

8. The method of claim 1 , wherein the die attach film comprises an epoxy.

9. A method of manufacturing a semiconductor package, the method comprising:

bonding a first side of a wafer comprising a plurality of semiconductor die to a first base frame through a die attach material;

singulating the plurality of semiconductor die;

bonding a second side of the plurality of semiconductor die opposite the first side to a second base frame through an additional die attach material;

applying a mold compound between the first base frame and the second base frame; and

singulating the first and second base frames to form a plurality of semiconductor packages.

10. The method of claim 9 , wherein the semiconductor package is a press fit package.

11. The method of claim 9 , wherein the first base frame comprises a plurality of terminals.

12. The method of claim 9 , wherein the second base frame comprises a plurality of terminals.

13. The method of claim 9 , wherein the wafer comprises a plurality of die pads, wherein the plurality of die pads are bonded to the first base frame.

14. The method of claim 9 , wherein both overmolding and underfilling are used to apply the mold compound.

15. The method of claim 9 , wherein the die attach film comprises solder.

16. The method of claim 9 , wherein the die attach film comprises epoxy.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047734, FRAME 0068 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064160/0027 →
SECURITY INTEREST Recorded Dec 6, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047734/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2018
From: TRUHITTE, DARRELL; LETTERMAN, JAMES P., JR.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044771/0649 →
Continuity (2)
Division 14341454 · Jul 25, 2014
Related Publication 20180174881A1 · Jun 21, 2018