Method of manufacturing a semiconductor device and a semiconductor device
In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.
1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked and protruding from an isolation insulating layer;
forming a sacrificial gate structure over the fin structure;
etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;
forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers;
etching the dielectric layer and part of the second semiconductor layers, thereby forming a second source/drain space; and
forming a source/drain epitaxial layer in the second source/drain space, wherein:
at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer,
at least one of the second semiconductor layers is separated from a bottom of the source/drain epitaxial layer by the dielectric layer, and
an upper surface of the isolation insulating layer is located at a level below a bottom of the source/drain epitaxial layer.
2. The method of claim 1 , wherein the dielectric layer includes a low-k dielectric material.
3. The method of claim 1 , further comprising, after the source/drain epitaxial layer is formed:
removing the sacrificial gate structure, thereby exposing a part of the fin structure;
removing the first semiconductor layers from the exposed fin structure, thereby forming channel layers including the second semiconductor layers; and
forming a gate dielectric layer and a gate electrode layer around the channel layers.
4. The method of claim 3 , wherein the gate electrode layer wraps around the at least one of the second semiconductor layers separated from the source/drain epitaxial layer.
5. The method of claim 1 , wherein the at least one of the second semiconductor layers separated from the source/drain epitaxial layer is located closer to a substrate than remaining second semiconductor layers contacting the source/drain epitaxial layer.
6. The method of claim 1 , wherein two or more of the second semiconductor layers are separated from the source/drain epitaxial layer.
7. The method of claim 6 , wherein only one of the second semiconductor layers is in contact with the source/drain epitaxial layer.
8. The method of claim 1 , wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.
9. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked and protruding from an isolation insulating layer;
forming a sacrificial gate structure over the fin structure;
etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;
forming a dielectric layer at the source/drain region, thereby covering the exposed second semiconductor layers;
partially etching the dielectric layer between adjacent second semiconductor layers, thereby forming a second source/drain space, at least one of the second semiconductor layers being exposed in and crossing the second source/drain space; and
forming a source/drain epitaxial layer in the second source/drain space, wherein:
the at least one of the second semiconductor layers exposed in the second source/drain space is in contact with the source/drain epitaxial layer,
at least one of the second semiconductor layers is not in contact with the source/drain epitaxial layer and separated from a bottom of the source/drain epitaxial layer by the dielectric layer, and
an upper surface of the isolation insulating layer is located at a level below the bottom of the source/drain epitaxial layer.
10. The method of claim 9 , wherein the dielectric layer includes a low-k dielectric material.
11. The method of claim 9 , further comprising, after the source/drain epitaxial layer is formed:
removing the sacrificial gate structure, thereby exposing a part of the fin structure;
removing the first semiconductor layers from the exposed fin structure, thereby forming channel layers including the second semiconductor layers; and
forming a gate dielectric layer and a gate electrode layer around the channel layers.
12. The method of claim 11 , wherein the gate electrode layer wraps around the at least one of the second semiconductor layers separated from the source/drain epitaxial layer.
13. The method of claim 9 , wherein the at least one of the second semiconductor layers separated from the source/drain epitaxial layer is located closer to a substrate than remaining second semiconductor layers contacting the source/drain epitaxial layer.
14. The method of claim 9 , wherein two or more of the second semiconductor layers are separated from the source/drain epitaxial layer.
15. The method of claim 14 , wherein only one of the second semiconductor layers is in contact with the source/drain epitaxial layer.
16. The method of claim 9 , wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.
17. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked on a bottom fin structure and protruding from an isolation insulating layer;
forming a sacrificial gate structure over the fin structure;
etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;
forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers;
etching part of the dielectric layer disposed between adjacent second semiconductor layers and part of the second semiconductor layers, thereby forming a second source/drain space; and
forming a source/drain epitaxial layer in the second source/drain space, wherein:
at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer,
at least one of the second semiconductor layers is not in contact with the source/drain epitaxial layer, and
an upper surface of the isolation insulating layer is located at a level below a bottom of the source/drain epitaxial layer and above an upper surface of the bottom fin structure.
18. The method of claim 17 , wherein the dielectric layer remains below the at least one of the second semiconductor layers not in contact with the source/drain epitaxial layer.
19. The method of claim 17 , wherein end faces of the second semiconductor layers except the at least one of the second semiconductor layers not in contact with the source/drain epitaxial layer contact the source/drain epitaxial layer.
20. The method of claim 17 , wherein a bottom of the source/drain epitaxial layer is in contact with the dielectric layer.