Method of manufacturing semiconductor devices having different gate dielectric thickness within one transistor
View Patent ↗In a method for manufacturing a semiconductor device, a fin structure is formed over a substrate, an isolation insulating layer is formed over the substrate such that an upper portion of the fin structure protrudes from the isolation insulating layer, a first dielectric layer is formed on the upper portion of the fin structure, a cover layer is formed on the first dielectric layer, the cover layer is partially removed from an upper part of the upper portion of the fin structure with the first dielectric layer, the first dielectric layer is removed from the upper part of the upper portion of the fin structure, a second dielectric layer is formed on the upper part of the upper portion of the fin structure, and a gate electrode is formed on the second dielectric layer and the first dielectric layer disposed on an lower part of the upper portion of the fin structure.
1. A semiconductor device, comprising:
a first fin structure and a second fin structure disposed over a substrate;
an isolation insulating layer, an upper portion of the first and second fin structures protruding from the isolation insulating layer;
a first dielectric layer disposed on a lower part of the upper portion of the first fin structure and disposed on a lower part and an upper part of the upper portion of the second fin structure;
a second dielectric layer disposed on an upper part of the upper portion of the first fin structure;
a first gate electrode disposed over the first and second dielectric layers disposed on the first fin structure; and
a second gate electrode disposed over the first dielectric layer disposed on the second fin structure,
wherein a thickness of the second dielectric layer is smaller than a thickness of the first dielectric layer disposed over the first fin structure and the second fin structure, and
wherein a height of the upper part of the upper portion is 40% to 60% of a height of the upper portion of the first and second fin structures measured from an upper surface of the isolation insulating layer to an uppermost surface of the first and second fin structures.
2. The semiconductor device of claim 1 , wherein the thickness of the second dielectric layer is 0.2 nm to 1.0 nm.
3. The semiconductor device of claim 1 , wherein the thickness of the first dielectric layer is 0.4 nm to 4.0 nm.
4. The semiconductor device of claim 1 , wherein at least the upper portion of the first fin structure includes SiGe.
5. The semiconductor device of claim 1 , wherein the first and second dielectric layers are made of silicon oxide.
6. The semiconductor device of claim 5 , further comprising a high-k dielectric layer disposed over the first and second dielectric layers.
7. A semiconductor device, comprising:
a first pair of fin structures disposed over a substrate;
an isolation insulating layer, upper portions of the first pair of fin structures protruding from the isolation insulating layer;
a first dielectric layer disposed on lower parts of the upper portions of the first pair of fin structures;
a second dielectric layer disposed on upper parts of the upper portions of the first pair of fin structures;
a first gate electrode disposed over the first and second dielectric layers of the first pair of fin structures;
a second pair of fin structures disposed over the substrate,
wherein upper portions of the second pair of fin structures protrude from the isolation insulating layer, and
the first dielectric layer is disposed on lower parts and upper parts of the upper portions of the second pair of fin structures; and
a second gate electrode disposed over the first dielectric layer of the second pair of fin structures,
wherein the first gate electrode includes a recess between the pair of fin structures,
wherein a thickness of the second dielectric layer is smaller than a thickness of the first dielectric layer disposed over the first and second pairs of fin structures, and
wherein a height of the upper parts of the upper portions is 30% to 70% of a height of the upper portions of the fin structures measured from an upper surface of the isolation insulating layer to uppermost surfaces of the first and second pairs of fin structures.
8. The semiconductor device of claim 7 , wherein the thickness of the second dielectric layer is 0.3 nm to 0.8 nm.
9. The semiconductor device of claim 8 , wherein the thickness of the first dielectric layer is 1.0 nm to 3.0 nm.
10. The semiconductor device of claim 7 , wherein the height of the upper parts of the upper portions is 40% to 60% of the height of the upper portions of the first and second pairs of fin structures measured from the upper surface of the isolation insulating layer to the uppermost surfaces of the first and second pairs of fin structures.
11. The semiconductor device of claim 7 , wherein the first and second dielectric layers are made of silicon oxide.
12. The semiconductor device of claim 7 , further comprising a high-k dielectric layer disposed over the first and second dielectric layers.
13. The semiconductor device of claim 7 , wherein the recess is V-shaped.
14. A semiconductor device, comprising:
a pair of first fin structures and a second fin structure, disposed over a substrate;
an isolation insulating layer, upper portions of the pair of first fin structure and an upper portion of the second fin structure protruding from the isolation insulating layer;
a first dielectric layer disposed on lower parts of the upper portions of the pair of first fin structures;
a second dielectric layer disposed on upper parts of the upper portions of the pair of first fin structures;
a third dielectric layer disposed on the upper portion of the second fin structure;
a first gate electrode disposed over the first and second dielectric layers of the pair of fin structures; and
a second gate electrode disposed over the third dielectric layer of the second fin structure,
wherein the first gate electrode includes a recess between the pair of first fin structures,
wherein a thickness of the second dielectric layer is smaller than a thickness of the first dielectric layer and a thickness of the third dielectric layer, and
wherein a height of the upper parts of the upper portions is 30% to 70% of a height of the upper portions of the fin structures measured from an upper surface of the isolation insulating layer to an uppermost surface of the pair of first fin structures and the second fin structure.
15. The semiconductor device of claim 14 , wherein the thickness of the second dielectric layer is 0.3 nm to 0.8 nm.
16. The semiconductor device of claim 15 , wherein the thickness of the first dielectric layer is 1.0 nm to 3.0 nm.
17. The semiconductor device of claim 14 , wherein the height of the upper parts of the upper portions is 40% to 60% of the height of the upper portions of the first fin structures measured from the upper surface of the isolation insulating layer to an uppermost surface of the first fin structures and the second fin structure.
18. The semiconductor device of claim 14 , wherein the first, second and third dielectric layers are made of silicon oxide.
19. The semiconductor device of claim 14 , further comprising a high-k dielectric layer disposed over the first and second dielectric layers, and on the third dielectric layer.
20. The semiconductor device of claim 14 , wherein the recess is V-shaped.