IP Library › Granted Patent US 10,250,198
Granted Patent B2
US 10,250,198 · App. 15/887,199 · Granted Apr 2, 2019

Methods of adjusting gain error in instrumentation amplifiers

Inventors: Serban Motoroiu (Campina, RO); Jim Nolan (Chandler, AZ)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H03F1/12H03F1/342H03F3/45179H03F3/45183H03F3/45672H03G1/0023H03G1/0029H03G1/0088H03F2200/258H03F2200/261H03F2203/45048H03F2203/45138H03F2203/45341H03F2203/45342H03F2203/45466H03F2203/45494H03F2203/45504H03F2203/45511H03F2203/45521
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Quick Facts
Patent No.
US 10,250,198
App. No.
15/887,199
Granted
Apr 2, 2019
Kind
B2
Abstract

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a trimming circuit that trims the back-bias voltages of the transistors in each transconductor. The trimming circuit includes a plurality of selectable resistors disposed in the signal path of the tail current in each transconductor. Each of the plurality of selectable resistors has a switch coupled to it. When a switch is closed, only the resistors up to the respective switch are in the signal path of the bulk-to-source voltage of the differentially paired transistors. The resistor trimming circuit reduces the mismatch between transconductances of the respective differential pair transistors, in turn reducing mismatch of the overall transconductances of the transconductors, and thereby reducing the CFIA's gain error.

Claims (71)

1. A method for gain error correction in a current-feedback instrumentation amplifier, said method comprising the steps of:

providing an input transconductor comprising

a first differential pair of transistors,

a first tail current source, and

a first trimming circuit coupled between the first tail current source and the first differential pair of transistors, and to a bulk of the first differential pair of transistors,

wherein the first trimming circuit varies a first back-bias voltage on the bulk of the first differential pair of transistors;

providing a feedback transconductor comprising

a second differential pair of transistors,

a second tail current source, and

a second trimming circuit coupled between the second tail current source and the second differential pair of transistors, and to a bulk of the second differential pair of transistors;

wherein the second trimming circuit varies a second back-bias voltage on the bulk of the second differential pair of transistors; and

adjusting the first and/or second trimming circuits to reduce gain error between the input transconductor and feedback transconductor.

2. The method according to claim 1 , further comprising the steps of:

providing first degeneration resistors coupled between the first differential pair of transistors and the first trimming circuit; and

providing second degeneration resistors coupled between the second differential pair of transistors and the second trimming circuit.

3. The method according to claim 1 , wherein the first and second trimming circuits comprise a plurality of series connected resistors and a plurality of switches coupled to the plurality of series connected resistors, whereby the first and second back-bias voltages are varied.

4. The method according to claim 3 , further comprising the step of storing open and closed states of the plurality of switches in a non-volatile memory.

5. The method according to claim 1 , further comprising the step of coupling the input and feedback transconductors to an amplifier.

6. The method according to claim 5 , further comprising the steps of:

coupling a feedback network between an output of the amplifier and inputs of the feedback transconductor; and

determining the current-feedback instrumentation amplifier gain with the feedback network.

7. The method according to claim 1 , further comprising the steps of:

providing a modulator circuit between the first and second tail current sources, and the first and second trimming circuits;

controlling the modulator circuit by alternating first and second phase states;

wherein

during the first phase state the modulator circuit couples the first tail current source to the first trimming circuit and the second tail current source to the second trimming circuit, and

during the second phase state the modulator circuit couples the first tail current source to the second trimming circuit, and the second tail current source to the first trimming circuit.

8. A current-feedback instrumentation amplifier having gain error correction, comprising:

an input transconductor comprising

a first differential pair of transistors,

a first tail current source, and

a first trimming circuit coupled between the first tail current source and the first differential pair of transistors, and to a bulk of the first differential pair of transistors;

wherein the first trimming circuit is configured to vary a first back-bias voltage on the bulk of the first differential pair of transistors;

a feedback transconductor comprising

a second differential pair of transistors,

a second tail current source, and

a second trimming circuit coupled between the second tail current source and the second differential pair of transistors, and to a bulk of the second differential pair of transistors;

wherein the second trimming circuit is configured to vary a second back-bias voltage on the bulk of the second differential pair of transistors; and

the first and/or second trimming circuits are adapted to be adjusted to reduce gain error between the input transconductor and feedback transconductor.

9. The current-feedback instrumentation amplifier according to claim 8 , further comprising:

first degeneration resistors coupled between the first differential pair of transistors and the first trimming circuit; and

second degeneration resistors coupled between the second differential pair of transistors and the second trimming circuit.

10. The current-feedback instrumentation amplifier according to claim 8 , wherein the first and second trimming circuits comprise a plurality of series connected resistors and a plurality of switches coupled to the plurality of series connected resistors, wherein the plurality of resistors and switches are adapted to vary the first and second back-bias voltages.

11. The current-feedback instrumentation amplifier according to claim 10 , further comprising a non-volatile memory adapted for storing open and closed states of the plurality of switches.

12. The current-feedback instrumentation amplifier according to claim 8 , further comprising an amplifier having inputs coupled to outputs from the input and feedback transconductors.

13. The current-feedback instrumentation amplifier according to claim 12 , further comprising a feedback network coupled between an output of the amplifier and inputs of the feedback transconductor.

14. The current-feedback instrumentation amplifier according to claim 12 , wherein the feedback network comprises:

a first feedback resistor;

a second feedback resistor; and

a voltage reference;

wherein

the first and second feedback resistors and the voltage reference are connected in series,

a first input of the feedback transconductor is coupled to a node between the second feedback resistor and the voltage reference,

a second input of the feedback transconductor is coupled to a node between the first feedback resistor and the second feedback resistor, and

the output of the amplifier is coupled to the first feedback resistor;

wherein gain is determined by a ratio of resistance values of the first and second feedback resistors.

15. The current-feedback instrumentation amplifier according to claim 8 , further comprising:

a modulator circuit coupled between the first and second tail current sources, and the first and second trimming circuits, wherein the modulator circuit is adapted to alternate between first and second phase states;

wherein during the first phase state the modulator circuit is adapted to couple the first tail current source to the first trimming circuit and the second tail current source to the second trimming circuit; and

wherein during the second phase state the modulator circuit is adapted to couple the first tail current source to the second trimming circuit, and the second tail current source to the first trimming circuit.

16. The current-feedback instrumentation amplifier according to claim 15 , wherein the modulator circuit comprises:

a first switch coupled between the first tail current source and the first degeneration resistors;

a second switch coupled between the first tail current source and the second degeneration resistors;

a third switch coupled between the second tail current source and the first degeneration resistors; and

a fourth switch coupled between the second tail current source and the second degeneration resistors;

wherein

the first and fourth switches are configured to close and the second and third switches are configured to open on a first phase state control signal; and

the second and third switches are configured to close and the first and fourth switches are configured to open on a second phase state control signal.

17. The current-feedback instrumentation amplifier according to claim 16 , wherein the first and second phase state control signals are from a clock generator, wherein the first phase state control signal is at a first logic level and the second phase state control signal is at a second logic level.

18. The current-feedback instrumentation amplifier according to claim 16 , wherein the first, second, third and fourth switches are metal oxide semiconductor field effect transistors (MOSFETs).

19. The current-feedback instrumentation amplifier according to claim 8 , wherein the input and feedback transconductors are fabricated on an integrated circuit die.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2018
From: MOTOROIU, SERBAN; NOLAN, JIM
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 045242/0932 →
Continuity (2)
Provisional Application 62500448 · May 2, 2017
Related Publication 20180323748A1 · Nov 8, 2018