Semiconductor integrated circuit device and wearable device
To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
1. A semiconductor integrated circuit device comprising:
a memory cell array which includes:
a plurality of memory cells, each of the memory cells having a P-type SOTB transistor and an N-type SOTB transistor;
a plurality of word lines coupled to the memory cells, respectively; and
a plurality of bit lines coupled to the memory cells, respectively;
a plurality of word drivers coupled to the word lines respectively, each of the word drivers having a P-type MOS transistor and an N-type MOS transistor,
wherein the semiconductor integrated circuit has a first mode and a second mode,
wherein a first voltage is supplied to a substrate of the P-type SOTB transistor, a second voltage is supplied to a substrate of the N-type SOTB transistor, a third voltage is supplied to a substrate of the P-type MOS transistor, and a fourth voltage is supplied to a substrate of the N-type MOS transistor when the semiconductor integrated circuit is in the first mode, and
wherein an operating frequency of the first mode is lower than that of the second mode.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the first and second voltages are not supplied to the substrates of the P-type and the N-type SOTB transistors when the semiconductor integrated circuit is in the second mode.
3. The semiconductor integrated circuit device according to claim 1 , further comprising:
a substrate bias generation circuit supplying the first, second, third and fourth voltages.
4. The semiconductor integrated circuit device according to claim 1 ,
wherein a static random access memory circuit includes the memory cell array and the word drivers and is coupled to a central processing unit via a bus,
wherein the central processing unit has a P-type MOS transistor and an N-type MOS transistor, and
wherein the third voltage is supplied to a substrate of the P-type MOS transistor of the central processing unit, and the fourth voltage is supplied to a substrate of the N-type MOS transistor of the central processing unit when the semiconductor integrated circuit is in the first mode.
5. The semiconductor integrated circuit device according to claim 4 , further comprising:
a mode designation circuit for selecting the first mode and the second mode based on a designation signal from the central processing unit.
6. The semiconductor integrated circuit device according to claim 1 ,
wherein a value of the first voltage is different from a value of the second voltage, and
wherein a value of the third voltage is different from a value of the fourth voltage.
7. The semiconductor integrated circuit device according to claim 1 ,
wherein the P-type SOTB transistor includes a gate electrode, a source region, a drain region, a channel region which forms a channel between the source region and the drain region, and a first region which faces the channel through an insulation film,
wherein a first substrate bias voltage is supplied to the first region,
wherein the N-type SOTB transistor includes a gate electrode, a source region, a drain region, a channel region which forms a channel between the source region and the drain region, and a second region which faces the channel through an insulation film, and
wherein a second substrate bias voltage is supplied to the second region.
8. A wearable device comprising the semiconductor integrated circuit device according to claim 1 .