IP Library Granted Patent US 11,049,863
Granted Patent B2
US 11,049,863 · App. 15/889,182 · Granted Jun 29, 2021

Semiconductor structure with capacitor landing pad and method of making the same

Inventors: Li-Wei Feng (Kaohsiung, TW); Shih-Fang Tzou (Tainan, TW); Chien-Ting Ho (Taichung, TW); Ying-Chiao Wang (Changhua County, TW); Yu-Ching Chen (Kaohsiung, TW); Hui-Ling Chuang (Changhua County, TW); Kuei-Hsuan Yu (New Taipei, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10855H01L27/10814H01L27/10823
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Quick Facts
Patent No.
US 11,049,863
App. No.
15/889,182
Granted
Jun 29, 2021
Kind
B2
Abstract

A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Claims (11)

1. A semiconductor structure with capacitor landing pads, comprising:

a substrate;

a capacitor contact plug disposed on the substrate;

a capacitor landing pad contacting and electrically connecting the capacitor contact plug;

a bit line disposed on the substrate;

a bit line mask contacting the bit line; and

a dielectric layer surrounding the capacitor landing pad, wherein the dielectric layer comprises a bottommost surface lower than a top surface of the bit line, and a topmost surface of the capacitor landing pad and a topmost surface of the dielectric layer are aligned, and a topmost surface of the bit line mask is lower than the topmost surface of the capacitor landing pad.

2. The semiconductor structure with capacitor landing pads of claim 1 , wherein a first distance is disposed between the topmost surface of the capacitor landing pad and a top surface of the substrate, a second distance is disposed between the top surface of the bit line and the top surface of the substrate, and the first distance is greater than the second distance.

3. The semiconductor structure with capacitor landing pads of claim 1 , wherein the dielectric layer forms a chessboard pattern.

4. The semiconductor structure with capacitor landing pads of claim 1 , wherein the bit line mask is between the capacitor landing pad and the bit line.

5. The semiconductor structure with capacitor landing pads of claim 1 , wherein the dielectric layer is in a shape of a meat cleaver including a handle and a blade, a topmost surface of the blade is aligned with the topmost surface of the capacitor landing pad, a bottommost surface of the handle is lower than the top surface of the bit line, and the blade is wider than the handle.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2018
From: FENG, LI-WEI; TZOU, SHIH-FANG; HO, CHIEN-TING; WANG, YING-CHIAO; CHEN, YU-CHING; CHUANG, HUI-LING; YU, KUEI-HSUAN
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 045663/0534 →
Priority Claims (1)
CN 201710102423.8 · Feb 24, 2017 · national
Continuity (1)
Related Publication 20180247943A1 · Aug 30, 2018
Cited By (2)
US 12,193,209 US 12,336,161