Semiconductor structure and manufacturing method thereof
A semiconductor structure includes: a substrate; a gate structure on the substrate; and an interconnect structure including a first interconnect sub-structure and a second interconnect sub-structure, where the second interconnect sub-structure protrudes from the first interconnect sub-structure. The first interconnect sub-structure is connected with the substrate, and the second interconnect sub-structure is connected with a top of the gate structure.
1. A semiconductor structure, comprising:
a substrate;
a gate structure on the substrate, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer; and
an interconnect structure comprising a first interconnect sub-structure and a second interconnect sub-structure, wherein the second interconnect sub-structure protrudes from the first interconnect sub-structure,
wherein the first interconnect sub-structure is connected with the substrate and in direct contact with a side surface of the gate electrode layer, and the second interconnect sub-structure is connected with a top of the gate structure and in direct contact with a top surface of the gate electrode layer.
2. The semiconductor structure of claim 1 , further comprising:
an isolation layer disposed on a side surface of the gate structure,
wherein the first interconnect sub-structure is in direct contact with the isolation layer.
3. The semiconductor structure of claim 1 , further comprising:
a first dielectric layer on the substrate,
wherein the gate structure and the interconnect structure are disposed in the first dielectric layer, and a top surface of the second interconnect sub-structure is lower than a top surface of the first dielectric layer.
4. The semiconductor structure of claim 3 , further comprising:
a second dielectric layer disposed on the first dielectric layer and covering the second interconnect sub-structure,
wherein a top surface of the first interconnect sub-structure is flush with a top surface of the second dielectric layer.
5. The semiconductor structure of claim 1 , further comprising:
a capacitor contact pad, wherein an etched bottom of the capacitor contact pad is flush with a top surface of the second interconnect sub-structure, and a top surface of the capacitor contact pad is flush with a top surface of the first interconnect sub-structure.
6. The semiconductor structure of claim 1 , wherein the gate structure and the interconnect structure form a part of a memory cell of a Static Random Access Memory (SRAM).
7. The semiconductor structure of claim 1 , wherein
the substrate comprises an isolation structure; and
a projection of the gate structure on the substrate at least partially covers the isolation structure.
8. A semiconductor structure, comprising:
a substrate;
a gate structure on the substrate;
an interconnect structure comprising a first interconnect sub-structure and a second interconnect sub-structure, wherein the second interconnect sub-structure protrudes from the first interconnect sub-structure; and
a capacitor contact pad;
wherein the first interconnect sub-structure is connected with the substrate, and the second interconnect sub-structure is connected with a top of the gate structure, wherein an etched bottom of the capacitor contact pad is flush with a top surface of the second interconnect sub-structure, and a top surface of the capacitor contact pad is flush with a top surface of the first interconnect sub-structure.