Extremely thin semiconductor-on-insulator with back gate contact
A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.
1. A method of forming a semiconductor structure comprising:
forming non-contiguous first conductivity type semiconductor regions entirely within a semiconductor base layer of a semiconductor-on-insulator substrate, wherein a gap comprising a semiconductor material portion of said semiconductor base layer is present between each non-contiguous first conductivity type semiconductor region, and wherein said semiconductor-on-insulator substrate further comprises at least one buried dielectric material layer located on a surface of the semiconductor base layer, and a semiconductor-on-insulator layer located on an uppermost surface of said at least one buried dielectric material layer;
patterning said semiconductor-on-insulator layer forming at least one first active device region and a second active device region, wherein said first active device region is located above one of said non-contiguous first conductivity type semiconductor regions and said second active device region is located atop another of said non-contiguous first conductivity type semiconductor regions, and wherein said first and second active device regions are both vertically offset from said gap;
forming a first transistor within said first active device region and a second transistor within said second active device region;
forming an interconnect structure straddling each of said first and second transistors; and
removing said semiconductor base layer of said semiconductor-on-insulator substrate stopping on a surface of each of said non-contiguous first conductivity type semiconductor regions and a surface of said at least one buried dielectric material layer.
2. The method of claim 1 , wherein each of said non-contiguous first conductivity type semiconductor regions has a surface in direct contact with a surface of the at least one buried dielectric material layer.
3. The method of claim 1 , wherein said forming said plurality of non-contiguous first conductivity type semiconductor regions comprises forming a patterned implantation mask on a surface of said semiconductor-on-insulator layer, wherein said patterned implantation mask protects at least one portion of said semiconductor-on-insulator layer, while leaving other portions of said semiconductor-on-insulator layer exposed, and implanting a first conductivity type dopant through said exposed portions of said semiconductor-on-insulator layer.
4. The method of claim 3 , wherein said first conductivity type dopant comprise a p-type dopant.
5. The method of claim 1 , wherein said removing said portion of said semiconductor base layer comprises a controlled spalling process.
6. The method of claim 5 , wherein said controlled spalling process comprises forming at least a stressor layer on an exposed surface of said interconnect structure.
7. The method of claim 6 , wherein said stressor layer comprises a metal.
8. The method of claim 5 , wherein said controlled spalling process is performed at room temperature or at a temperature below room temperature.
9. The method of claim 5 , wherein after said controlled spalling process a spalled portion of said semiconductor base layer remains, and wherein etching is employed to remove the spalled portion of said semiconductor base layer.
10. The method of claim 1 , wherein said forming said interconnect structure includes forming metal contacts within a dielectric material.
11. The method of claim 10 , wherein some of said metal contacts extend to a surface of each of said non-contiguous first conductivity type semiconductor regions.
12. The method of claim 1 , wherein said removing said semiconductor base layer comprises a planarization process, followed by an isotropic etching process.
13. The method of claim 1 , wherein said removing said semiconductor base layer comprises isotropic etching.
14. The method of claim 1 , further comprising forming a passivation layer on at least exposed surfaces of each of said non-contiguous first conductivity type semiconductor regions.
15. The method of claim 1 , wherein a bottommost surface of said least one buried dielectric material layer is in direct contact with an uppermost surface of each of said non-contiguous first conductivity type semiconductor regions.
16. The method of claim 1 , wherein each of said non-contiguous first conductivity type semiconductor regions comprises a p-type dopant atom.
17. The method of claim 1 , wherein each of said non-contiguous first conductivity type semiconductor regions comprises a p-type dopant atom.
18. The method of claim 1 , wherein an uppermost surface of each of said non-contiguous first conductivity type semiconductor regions is coplanar with an uppermost surface of said semiconductor material portion of said semiconductor base layer.