IP Library Granted Patent US 10,491,116
Granted Patent B2
US 10,491,116 · App. 15/892,622 · Granted Nov 26, 2019

Fast transient response circuit

Inventor: Keith E. Curtis (Gilbert, AZ)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H02M3/156H02M2001/0019H02M2001/0025H02M2003/1566
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Quick Facts
Patent No.
US 10,491,116
App. No.
15/892,622
Granted
Nov 26, 2019
Kind
B2
Abstract

A circuit includes a reference voltage, a switched mode power supply (SMPS) loop filter circuit configured to provide an inductor current limit based on the reference voltage, and a trigger circuit configured to enable or disable the SMPS loop filter circuit. When the SMPS loop filter circuit is enabled, an output of the circuit is based on output of the SMPS loop filter circuit and output voltage of the SMPS. When the SMPS loop filter circuit is disabled, the SMPS current control circuit output is based on an estimated current limit that is increased when load current demand will increase and decreased when load current demand will decrease.

Claims (48)

1. A switched-mode power supply (SMPS) control circuit, comprising:

a loop control circuit comprising:

an operational amplifier having:

first and second inputs; and

an output configured to be enabled and disabled; and

a loop filter coupled between the first input and the output of the operational amplifier, wherein the first input of the operation amplifier and the loop filter are coupled to a voltage output of an SMPS;

a first voltage reference coupled to the second input of the operational amplifier;

a voltage comparator having first and second inputs and an output, wherein: the first input is coupled to a current-to-voltage circuit configured to measure output current of the SMPS, and the second input is coupled to the output of the operational amplifier, whereby voltage applied to an inductor of the SMPS is configured to be controlled by the output of the voltage comparator; and

a second voltage reference having an output coupled to the operational amplifier and the second input of the comparator, wherein when the operational amplifier output is disabled the second voltage reference is configured to supply a voltage to the second input of the voltage comparator instead of the operational amplifier output supplying voltage to the second input of the voltage comparator, whereby the voltage comparator is configured to use the output of the second voltage reference rather than the output of the operational amplifier to control the voltage to the SMPS inductor; and

a timer including:

an input configured to be triggered by an event; and

an output configured to enable and disable the output of the operational amplifier;

wherein the event is an increase or a decrease in a load current of the SMPS;

wherein:

the time to be counted by the timer is programmable; and

the time to be counted by the timer is determined by an anticipated SMPS output current increase or decrease.

2. The SMPS control circuit according to claim 1 , wherein:

the event is an increase in the SMPS load current; and

the output of the second voltage reference supplies the voltage to the second input of the voltage comparator instead of the operational amplifier, whereby a voltage from the second voltage reference is greater than the voltage from the operational amplifier when the operational amplifier is enabled.

3. The SMPS control circuit according to claim 2 , wherein a loop filter voltage charges up during the current increase event.

4. The SMPS control circuit according to claim 1 , wherein:

the event is a decrease in the SMPS load current; and

the output of the second voltage reference supplies the voltage to the second input of the voltage comparator instead of the operational amplifier, whereby the voltage from the second voltage reference is less than a voltage from the operational amplifier when the operational amplifier is enabled.

5. The SMPS control circuit according to claim 4 , wherein a loop filter voltage discharges down during the current decrease event.

6. The SMPS control circuit according to claim 1 , wherein the first inputs of the operational amplifier and voltage comparator are negative inputs, and the second inputs of the operational amplifier and voltage comparator are positive inputs.

7. The SMPS control circuit according to claim 1 , wherein the loop filter comprises at least one resistor and at least one capacitor.

8. The SMPS control circuit according to claim 1 , wherein the first voltage reference comprises a fixed voltage reference and a first digital-to-analog converter (DAC) having an output coupled to the second input of the operational amplifier.

9. The SMPS control circuit according to claim 8 , wherein the first DAC is programmable for adjusting a voltage to the second input of the operational amplifier.

10. The SMPS control circuit according to claim 1 , wherein the second voltage reference comprises a second DAC and is programmable.

11. The SMPS control circuit according to claim 1 , wherein the second voltage reference is programmed to supply a voltage that corresponds to an estimated increased load current.

12. The SMPS control circuit according to claim 1 , wherein the second voltage reference is programmed to supply a voltage that corresponds to an estimated decreased load current.

13. The SMPS control circuit according to claim 1 , wherein the loop filter is charged or discharged by an increase or decrease, respectively, of the voltage from the second voltage reference during the event.

14. The SMPS control circuit according to claim 1 , wherein the operational amplifier comprises a tri-state output, wherein when the tri-state output is disabled it is at a high impedance and does not affect the voltage from the second voltage reference.

15. A method for controlling a switched-mode power supply (SMPS), said method comprising the steps of:

providing a control loop including a comparator and an operational amplifier, wherein:

the operational amplifier includes an output that can be enabled and disabled; and

the control loop compares a SMPS output voltage to a first voltage reference and provides a control voltage from the output of the operational amplifier to the comparator that controls voltage to an inductor of the SMPS based upon the control voltage and an output current of the SMPS;

providing a timer having an input coupled to a trigger signal and an output coupled to the operational amplifier, wherein:

when the timer is not timing, the output of the operational amplifier is enabled; and

when the timer is timing, the output of the operational amplifier is disabled; and

providing a second voltage reference that is coupled to the comparator when the output of the operational amplifier is disabled;

wherein:

the trigger signal is based on an event that is an increase or a decrease in the SMPS load current;

the time to be counted by the timer is programmable; and

the time to be counted by the timer is determined by an anticipated SMPS output current increase or decrease.

16. The method according to claim 15 , wherein the trigger signal is in response to a current load change event of the SMPS.

17. The method according to claim 16 , wherein a voltage from the second voltage reference is greater than the control voltage from the operational amplifier during a current load increase event.

18. The method according to claim 16 , wherein a voltage from the second voltage reference is less than the control voltage from the operational amplifier during a current load decrease event.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2018
From: CURTIS, KEITH E.
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 044879/0701 →
Continuity (2)
Provisional Application 62456748 · Feb 9, 2017
Related Publication 20180226875A1 · Aug 9, 2018