Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system

1. A method for fabricating a negative capacitance steep-switch transistor comprising:

receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, a shallow trench isolation (STI) layer disposed upon the substrate, and an inter-layer dielectric disposed on the trench contact and the cap;

forming a source/drain recess in the inter-layer dielectric extending to the trench contact;

forming a gate recess in the inter-layer dielectric extending to the gate;

depositing a ferroelectric material within the gate recess;

forming a source/drain contact within the source/drain recess in contact with the trench contact;

forming a gate contact within the gate recess in contact with the ferroelectric material;

forming a contact recess in a portion of the source/drain contact;

depositing a bi-stable resistive system (BRS) material in the contact recess in contact with the portion of the source/drain contact; and

forming a metallization layer contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

2. The method of claim 1 , wherein depositing the ferroelectric material within the gate recess further comprises:

conformally depositing the ferroelectric material upon a top surface of the inter-layer dielectric, the S/D recess, and the gate recess;

depositing an organic planarization layer (OPL) to a bottom portion of the gate recess to mask the bottom portion of the gate recess;

etching the ferroelectric material except for the ferroelectric material masked by the OPL in the bottom portion of the gate recess; and

stripping the OPL from the gate recess.

3. The method of claim 1 , wherein the source/drain recess and the gate recess are formed in the inter-layer dielectric by a reactive ion etching (RIE) process.

4. The method of claim 1 , wherein the BRS material comprises an insulator-to-metal transition (IMT) material.

5. The method of claim 4 , wherein depositing the BRS material in the source/drain recess includes depositing the IMT material in contact with the portion of the source/drain contact.

6. The method of claim 4 , further comprising:

removing a portion of the IMT material outside of the source/drain recess using a planarization process.

7. The method of claim 6 , wherein the planarization process includes a chemical mechanical planarization (CMP) process.

8. The method of claim 1 , wherein the BRS material comprises a threshold-switching selector.

9. The method of claim 8 , wherein depositing the BRS material in the source/drain recess comprises:

depositing an oxide layer within the recess; and

forming a top electrode within the recess upon the oxide layer.

10. The method of claim 1 , further comprising:

applying an insulation cap layer to the structure; and

depositing a dielectric layer upon the insulation layer, the metallization layer contact being formed through the insulation cap layer and the dielectric layer.

11. An apparatus comprising:

a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, a shallow trench isolation (STI) layer disposed upon the substrate, and an inter-layer dielectric disposed on the trench contact and the cap;

a source/drain recess formed in the inter-layer dielectric extending to the trench contact;

a gate recess formed in the inter-layer dielectric extending to the gate;

a ferroelectric material deposited within the gate recess;

a source/drain contact formed within the source/drain recess in contact with the trench contact;

a gate contact formed within the gate recess in contact with the ferroelectric material;

a contact recess formed in a portion of the source/drain contact;

a bi-stable resistive system (BRS) material deposited in the contact recess in contact with the portion of the source/drain contact; and

a metallization layer contact formed upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

12. The apparatus of claim 11 , wherein the ferroelectric material is deposited within the gate recess by:

conformally depositing the ferroelectric material upon a top surface of the inter-layer dielectric, the S/D recess, and the gate recess;

depositing an organic planarization layer (OPL) to a bottom portion of the gate recess to mask the bottom portion of the gate recess;

etching the ferroelectric material except for the ferroelectric material masked by the OPL in the bottom portion of the gate recess; and

stripping the OPL from the gate recess.

13. The apparatus of claim 11 , wherein the source/drain recess and the gate recess are formed in the inter-layer dielectric by a reactive ion etching (RIE) process.

14. The apparatus of claim 11 , wherein the BRS material comprises an insulator-to-metal transition (IMT) material.

15. The apparatus of claim 14 , wherein the BRS material in the source/drain recess is deposited by depositing the IMT material in contact with the portion of the source/drain contact.

16. The apparatus of claim 14 , wherein a portion of the IMT material outside of the source/drain recess is removed using a planarization process.

17. The apparatus of claim 16 , wherein the planarization process includes a chemical mechanical planarization (CMP) process.

18. A computer usable program product comprising one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising:

program instructions to receive a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, a shallow trench isolation (STI) layer disposed upon the substrate, and an inter-layer dielectric disposed on the trench contact and the cap;

program instructions to form a source/drain recess in the inter-layer dielectric extending to the trench contact;

program instructions to form a gate recess in the inter-layer dielectric extending to the gate;

program instructions to deposit a ferroelectric material within the gate recess;

program instructions to form a source/drain contact within the source/drain recess in contact with the trench contact;

program instructions to form a gate contact within the gate recess in contact with the ferroelectric material;

program instructions to form a contact recess in a portion of the source/drain contact;

program instructions to deposit a bi-stable resistive system (BRS) material in the contact recess in contact with the portion of the source/drain contact; and

program instructions to form a metallization layer contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

19. The computer usable program product of claim 18 , wherein the computer usable code is stored in a computer readable storage device in a data processing system, and wherein the computer usable code is transferred over a network from a remote data processing system.

20. The computer usable program product of claim 15 , wherein the computer usable code is stored in a computer readable storage device in a server data processing system, and wherein the computer usable code is downloaded over a network to a remote data processing system for use in a computer readable storage device associated with the remote data processing system.