Metal ferroelectric insulator metal stack in RRAM
A memory structure that includes a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer. At least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage. A thickness of the ferroelectric dielectric layer and the paraelectric dielectric layer results in simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer for the formation of conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance. The memory structure also includes a first electrode at a first end of the dielectric stack, and a second electrode at a second end of the dielectric stack. The applied voltage is applied to the memory structure through at least one of the first electrode and the second electrode.
1 . A memory structure comprising:
a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer,
wherein the paraelectric dielectric layer comprises a hafnium containing oxide or a zirconium containing oxide,
wherein at least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage, and
wherein a thickness of the ferroelectric dielectric layer and a thickness of the paraelectric dielectric layer results in simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer for formation of conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance;
a first electrode at a first end of the dielectric stack; and
a second electrode at a second end of the dielectric stack,
wherein the applied voltage is applied to the memory structure through at least one of the first electrode and the second electrode.
2 . The memory structure of claim 1 , wherein the first electrode is a metal nitride comprising:
tantalum nitride,
titanium nitride, or
a combination thereof.
3 . The memory structure of claim 1 , wherein the ferroelectric dielectric layer includes a hafnium containing oxide comprising:
hafnium zirconium oxide,
hafnium silicon oxide, or
hafnium aluminum oxide.
4 . The memory structure of claim 1 , wherein the thickness of the ferroelectric dielectric layer is at least twice the thickness of the paraelectric dielectric layer.
5 . The memory structure of claim 1 , wherein the first electrode includes a metal comprising:
tantalum nitride,
titanium nitride, or
a combination thereof.
6 . An electrical device structure comprising:
a memory device region comprising at least one memory device including a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer, wherein at least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage that is employed for dielectric breakdown in formation of conductive filaments through the dielectric stack; and
a semiconductor device region comprising at least one semiconductor device that operates at an operation voltage that is less than the applied voltage that results in the formation of the conductive filaments in the memory device region.
7 . The electrical device structure of claim 6 , wherein a thickness of the ferroelectric dielectric layer and a thickness of the paraelectric dielectric layer facilitates simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer of the dielectric stack for the formation of the conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance.
8 . The electrical device structure of claim 6 , wherein the at least one memory device is a resistive random access memory (ReRAM) device.
9 . The electrical device structure of claim 6 , wherein the at least one semiconductor device comprises:
a planar field effect transistor (FET),
a fin type field effect transistor (FinFET),
a gate all around FET,
a stack nanosheet FET,
a vertical field effect transistor (VFET), or
a combination thereof.
10 . The electrical device structure of claim 6 , wherein the ferroelectric dielectric layer includes a hafnium containing oxide comprising:
hafnium zirconium oxide,
hafnium silicon oxide, or
hafnium aluminum oxide.
11 . The electrical device structure of claim 6 , wherein the paraelectric dielectric layer comprises a hafnium containing oxide or a zirconium containing oxide.
12 . The electrical device structure of claim 6 , wherein a thickness of the ferroelectric dielectric layer is at least twice a thickness of the paraelectric dielectric layer.
13 . The electrical device structure of claim 6 , wherein the at least one memory device comprises an electrode having a metal nitride composition comprising:
tantalum nitride,
titanium nitride, or
a combination thereof.