IP Library › Granted Patent US 10,475,514

Granted Patent B2

US 10,475,514 · App. 15/976,315 · Granted Nov 12, 2019

Nonvolatile digital computing with ferroelectric FET

Inventors: Xueqing Li (State College, PA); Sumitha George (State College, PA); John Sampson (State College, PA); Sumeet Gupta (State College, PA); Suman Datta (South Bend, IN); Vijaykrishnan Narayanan (State College, PA); Kaisheng Ma (State College, PA)

Assignee: The Penn State Research Foundation

G11C14/0072 G11C11/1675 G11C11/1693 G11C11/223 G11C11/2275 G11C11/2293 G11C13/0002 G11C13/0007 G11C13/0061 G11C13/0069 G11C14/009 G11C14/0054 G11C14/0081 H01L29/78391

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Quick Facts

Patent No.: US 10,475,514
App. No.: 15/976,315
Granted: Nov 12, 2019
Kind: B2

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Abstract

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I DS -V G hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I DS states at V G =0.

Claims (182)

1. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:

the circuit topology is configured as a latch configured to have a differential-driving input pair D/DN;

the latch comprising:

a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;

a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;

a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;

a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;

a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;

a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;

a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;

an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 5 -drain;

each of M 1 , M 2 , M 3 , M 4 , M 7 , and M 8 is a metal oxide semiconductor field effect transistor (MOSFET);

each of M 5 and M 6 is a FeFET;

M 1 -drain being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, a data output Q, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, a data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 1 -gate being connected to a clock driver CLK;

M 1 -source being connected to a data input D;

M 2 -drain being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, data output Q, M 1 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 2 -gate being connected to M 1 -gate;

M 2 -source being connected to a data input DN;

M 3 -drain being connected to a voltage supply V DD ;

M 3 -gate being connected to M 3 -source, M 4 -source, M 4 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 3 -source being connected to M 3 -gate, M 4 -source, M 4 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 4 -drain being connected to V DD ;

M 4 -gate being connected to M 3 -source, M 4 -source, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 4 -source being connected to M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 5 -drain be connected to M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 5 -gate being connected to M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -drain, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 5 -source being connected to M 7 -drain;

M 6 -drain can being connected to M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 5 -drain, M 6 -gate, and M 8 -gate;

M 6 -gate being connected to M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 5 -drain, M 6 -drain, and M 8 -gate;

M 6 -source being connected to M 8 -drain;

M 7 -drain being connected to M 8 -source;

M 7 -gate being connected to M 6 -gate, M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 5 -drain, data output QN, M 5 -drain, M 6 -drain, and M 8 -gate;

M 7 -source being connected to ground, GND;

M 8 -drain being connected to M 6 -source;

M 8 -gate being connected to M 7 -gate, M 6 -gate, M 4 -source, M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 5 -drain, data output QN, M 5 -drain, and M 6 -drain; and

M 8 -source being connected to GND.

2. A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias, wherein:

the circuit topology is configured as a D-Flip Flop (DFF);

the DFF comprising a master latch, a slave latch, and a backup and restore circuit (B&R circuit);

the slave latch comprising:

a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;

a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;

a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;

a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;

a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;

a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;

a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;

an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 8 -drain;

each of M 1 , M 2 , M 3 , M 4 , M 7 , and M 8 is a metal oxide semiconductor field effect transistor (MOSFET);

each of M 5 and M 6 is a FeFET;

M 1 -drain being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, a data output Q, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, a data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 1 -gate being connected to a clock driver CLK;

M 1 -source being connected to a data input D;

M 2 -drain being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, data output Q, M 1 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 2 -gate being connected to M 1 -gate;

M 2 -source being connected to a data input DN;

M 3 -drain being connected to a voltage supply V DD ;

M 3 -gate being connected to M 3 -source, M 4 -source, M 4 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 3 -source being connected to M 3 -gate, M 4 -source, M 4 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 4 -drain being connected to V DD ;

M 4 -gate being connected to M 3 -source, M 4 -source, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 4 -source being connected to M 3 -source, M 4 -gate, M 3 -gate, data output Q, M 1 -drain, M 2 -drain, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate;

M 5 -source being connected to M 7 -drain;

M 6 -source being connected to M 8 -drain;

M 7 -drain being connected to M 5 -source;

M 7 -source being connected to ground, GND;

M 8 -drain being connected to M 6 -source;

M 8 -source being connected to GND.

3. The NVM device recited in claim 2 , wherein:

M 1 is replaced with a first slave transmission gate, S GATE1 ;

M 2 is replaced with a second slave transmission gate, S GATE2 ;

output of S GATE1 being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, data output Q, S GATE2 output, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; and

output of S GATE2 being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, data output Q, S GATE1 output, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate.

4. The NVM device recited in claim 3 , wherein the master latch is connected to the slave latch via S GATE1 and S GATE2 .

5. The NVM device recited in claim 4 , wherein:

the master latch has a first master transmission gate M GATE1 , a first master inverter, M INV1 , a second master inverter, M INV2 , and a second master transmission gate, M GATE2 ;

input of M GATE1 being connected to a data input signal, D;

output of M GATE1 being connected to input of M INV1 and input of S GATE 1;

input of M INV1 being connected to output of M GATE1 ;

output of M INV1 being connected to input of M INV2 and input of S GATE2 ;

input of M INV2 being connected to output of M INV1 ;

output of M INV2 being connected to input of M GATE2 ;

input of M GATE2 being connected to output of M INV2 ; and

output of M GATE2 being connected to input of M GATE1 and output of M INV1 .

6. The NVM device recited in claim 2 , wherein:

M 1 is replaced with a first slave inverter, S INV1 :

M 2 is replaced with a second slave inverter, S INV2 ;

output of S INV1 being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, data output Q, S INV2 output, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate; and

output of S INV2 being connected to M 3 -gate, M 3 -source, M 4 -source, M 4 -gate, data output Q, S INV1 output, M 5 -gate, M 7 -gate, M 5 -drain, data output QN, M 6 -drain, M 6 -gate, and M 8 -gate.

7. The NVM device recited in claim 6 , wherein the master latch is connected to the slave latch via S INV1 and S INV2 .

8. The NVM device recited in claim 7 , wherein: