Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins

1. A method for forming a finFET device, comprising:

forming an n-doped and a p-doped region in a semiconductor wafer;

forming a layer of silicon germanium above both the n-doped and p-doped regions;

removing a portion of the silicon germanium layer above the p-doped region to create a first recess;

forming a layer of silicon in the first recess;

etching away at least a portion of the silicon layer and the underlying p-doped region;

etching away at least a portion of the silicon germanium layer and the underlying n-doped region;

forming fins of the finFET transistor from the unetched silicon and silicon germanium layers; and

forming a shallow trench isolation dielectric in the etched away portion of the silicon germanium layer and the underlying n-doped region and in the etched away portion of the silicon layer and the underlying p-doped region.

2. The method of claim 1 , further comprising forming a silicon carbon layer intermediate the layer of silicon germanium and the n-doped and p-doped regions having a carbon concentration in a range of 0.05% to 1% and a thickness in a range of 2 nm to 50 nm.

3. The method of claim 1 , further comprising implanting p-type dopants into the first recess after forming the first recess and prior to forming a layer of silicon in the first recess.

4. The method of claim 1 , further comprising forming a silicon carbon layer intermediate the layer of silicon and the n-doped and p-doped regions.

5. The method of claim 4 , wherein forming the layer of silicon carbon intermediate the layer of silicon and the n-doped and p-doped regions further comprises forming a layer of silicon carbon having a carbon concentration in the range of 0.1% to 0.4% and a thickness in a range of 5 nm to 20 nm.

6. The method of claim 4 , wherein removing the portion of the silicon germanium layer above the p-doped region to create the first recess further comprises etching the silicon germanium layer until the etching process reaches the silicon carbon layer.

7. The method of claim 1 , wherein removing the portion of the silicon germanium layer above the p-doped region to create the first recess further comprises etching the silicon germanium layer until the etching process reaches the p-doped region.

8. The method of claim 1 , wherein forming the p-doped region in the semiconductor wafer further comprises forming the p-doped region in the semiconductor wafer by patterned ion implantation of at least one p-type dopant from the group of boron (B), gallium (Ga), and indium (In) using a peak dopant concentration in a range of 1e18 atoms/cm 3 to 2e19 atoms/cm 3 .

9. The method of claim 1 , wherein forming the n-doped region in the semiconductor wafer further comprises forming the n-doped region in the semiconductor wafer by patterned ion implantation of at least one n-type dopant from the group of phosphorus (P), arsenic (As), and antimony (Sb) using a peak dopant concentration in a range 1e18 atoms/cm 3 to 2e19 atoms/cm 3 .

10. The method of claim 1 , wherein forming a layer of silicon germanium above the n-doped and p-doped regions further comprises forming an epitaxial silicon germanium layer having a thickness in a range of 30 nm to 80 nm.

11. The method of claim 1 , further comprising implanting n-type dopants into the first recess after forming the first recess and prior to forming a layer of silicon in the first recess.

12. The method of claim 1 , wherein forming a silicon layer further comprises forming an epitaxial silicon layer grown selectively on exposed crystalline silicon germanium regions and having a thickness in a range of 30 nm to 80 nm.

13. The method of claim 1 , wherein etching away at least a portion of the silicon layer and the underlying p-doped region, and etching away at least a portion of the silicon germanium layer and the underlying n-doped region further comprises using a single etching process to etch away at least a portion of the silicon layer and the underlying p-doped region and etch away at least a portion of the silicon germanium layer and the underlying n-doped region.

14. A method for forming a finFET device, comprising:

forming a silicon substrate having an n-doped region and a p-doped region;

forming at least one fin comprised of epitaxial silicon and having a first channel above the p-doped region;

forming at least one fin comprised of epitaxial silicon germanium and having a second channel above the n-doped region;

forming a first channel region in the epitaxial silicon fin having an average p-dopant concentration at least a factor of about 2 lower than an average p-dopant concentration of a region located at about 0 to about 40 nm beneath the first channel region; and

forming a second channel region in the epitaxial silicon germanium fin having an average n-dopant concentration at least a factor of about 2 lower than an average n-dopant concentration of a region located at about 0 to about 50 nm beneath the second channel region.

15. The method of claim 14 , further comprising implanting at least one p-type dopant from the group of B, Ga, and In within the p-doped region, wherein the average dopant concentration over about the top 50 nm of the p-doped region is between about 1e18 and about 6e18 atoms/cm 3 .

16. The method of claim 14 , wherein a dopant profile in at least one of the p-type doped region and the n-type doped region has a peak concentration at a location in a range of about 0 to about 30 nm below the first channel region and the second channel region.

17. The method of claim 14 , further comprising implanting at least one n-type dopant from the group of P, As and Sb within the n-doped region, wherein the average dopant concentration over about the top 50 nm of the n-doped region is between about 1e18 and about 6e18 atoms/cm 3 .

18. The method of claim 14 , wherein the silicon germanium fin has a germanium concentration of about 20 to about 50%.

19. A method for forming a finFET device, comprising:

forming an n-doped and a p-doped region in a semiconductor wafer;

forming a layer of silicon germanium above both the n-doped and p-doped regions;

removing a portion of the silicon germanium layer above the p-doped region to create a first recess;

implanting p-type dopants into the first recess after forming the first recess;

forming a layer of silicon in the first recess;

etching away at least a portion of the silicon layer and the underlying p-doped region;

etching away at least a portion of the silicon germanium layer and the underlying n-doped region;

forming fins of the finFET transistor from the unetched silicon and silicon germanium layers; and

forming a shallow trench isolation dielectric in the etched away portion of the silicon germanium layer and the underlying n-doped region and in the etched away portion of the silicon layer and the underlying p-doped region.

20. The method of claim 19 , further comprising forming a silicon carbon layer intermediate the layer of silicon germanium and the n-doped and p-doped regions having a carbon concentration in a range of 0.05% to 1% and a thickness in a range of 2 nm to 50 nm.