Method of forming complementary nano-sheet/wire transistor devices with same depth contacts

1. A device comprising:

a first nano-sheet of a first semiconductor material;

first source/drain regions positioned adjacent ends of the first nano-sheet;

a first dielectric material positioned above the first source/drain regions;

a second nano-sheet of a second semiconductor material positioned above the first nano-sheet;

second source/drain regions positioned adjacent ends of the second nano-sheet and above the first dielectric material;

a gate structure having a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet; and

a first source/drain contact contacting a first portion of the second source/drain regions in a first region where the second source/drain regions do not vertically overlap the first source/drain regions, wherein the first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the second source/drain regions vertically overlap the first source/drain regions.

2. The device of claim 1 , further comprising a second source/drain contact contacting a first portion of the first source/drain regions and a second portion of the second source/drain regions in the second region.

3. The device of claim 2 , further comprising a third source/drain contact contacting a second portion of the first source/drain regions in a third region where the second source/drain regions do not vertically overlap the first source/drain regions.

4. The device of claim 3 , wherein the second and third source/drain contacts have the first depth.

5. The device of claim 1 , further comprising:

a second source/drain contact contacting a second portion of the second source/drain regions in the first region on an opposite side of the gate structure compared to the first source/drain contact;

a third source/drain contact contacting a first portion of the first source/drain regions in a third region where the second source/drain regions do not vertically overlap the first source/drain regions; and

a fourth source/drain contact contacting a second portion of the first source/drain regions in the third region on an opposite side of the gate structure compared to the third source/drain contact.

6. The device of claim 1 , further comprising a second source/drain contact contacting a first portion of the first source/drain regions in a third region where the second source/drain regions do not vertically overlap the first source/drain regions.

7. The device of claim 6 , wherein the second source/drain contact has the first depth.

8. The device of claim 1 , wherein the first source/drain regions have a first conductivity type, the second source/drain regions have a second conductivity type different than the first conductivity type, the first portion includes a first work function material, and the second portion includes a second work function material different than the first work function material, wherein the first and second work function materials are configured to provide a first threshold voltage associated with the first portion and the first nano-sheet substantially equal to a second threshold voltage associated with the second portion and the second nano-sheet.

9. The device of claim 1 , wherein the first source/drain regions have a first conductivity type, the second source/drain regions have a second conductivity type different than the first conductivity type, and the first semiconductor material differs from the second semiconductor material.

10. The device of claim 9 , wherein a first germanium concentration of the first semiconductor material differs from a second germanium concentration of the second semiconductor material.

11. A method, comprising:

forming a stack of semiconductor material layers above a substrate, the stack including at least a first nano-sheet of a first semiconductor material and a second nano-sheet of a second semiconductor material;

forming first source/drain regions adjacent ends of the first nano-sheet;

removing a first portion of the first source/drain regions in a first contact region;

forming a first dielectric material above the first source/drain regions and in the first contact region;

forming second source/drain regions adjacent ends of the second nano-sheet and above the first dielectric material, wherein a portion of the second source/drain regions is positioned in the first contact region;

forming a gate structure having a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet;

forming a first source/drain contact contacting a second portion of the second source/drain regions in the first contact region, wherein the first source/drain contact has a first depth that extends below an upper surface of the first source/drain regions in a second contact region where the second source/drain regions vertically overlap the first source/drain regions.

12. The method of claim 11 , further comprising forming a second source/drain contact contacting a first portion of the first source/drain regions and a third portion of the second source/drain regions in the second contact region.

13. The method of claim 12 , further comprising:

removing a fourth portion of the second source/drain regions in a third contact region; and

forming a third source/drain contact contacting a second portion of the first source/drain regions in the third contact region.

14. The method of claim 13 , wherein the second and third source/drain contacts have the first depth.

15. The method of claim 11 , further comprising:

forming a second source/drain contact contacting a third portion of the second source/drain regions in the first contact region on an opposite side of the gate structure compared to the first source/drain contact;

forming a third source/drain contact contacting a first portion of the first source/drain regions in a third contact region where the second source/drain regions do not vertically overlap the first source/drain regions; and

forming a fourth source/drain contact contacting a second portion of the first source/drain regions in the third contact region on an opposite side of the gate structure compared to the third source/drain contact.

16. The method of claim 11 , further comprising:

removing a third portion of the second source/drain regions in a third contact region; and

forming a second source/drain contact contacting a first portion of the first source/drain regions in the third contact region.

17. The method of claim 16 , wherein the second source/drain contact has the first depth.

18. The method of claim 11 , wherein the first source/drain regions have a first conductivity type, the second source/drain regions have a second conductivity type different than the first conductivity type, and forming the gate structure further comprises forming a first work function material contacting the first nano-sheet and forming a second work function material different than the first work function material contacting the second nano-sheet, wherein the first and second work function materials are configured to provide a first threshold voltage associated with the first portion and the first nano-sheet substantially equal to a second threshold voltage associated with the second portion and the second nano-sheet.

19. The method of claim 11 , wherein the first source/drain regions have a first conductivity type, the second source/drain regions have a second conductivity type different than the first conductivity type, and the first semiconductor material differs from the second semiconductor material.

20. The method of claim 19 , wherein a first germanium concentration of the first semiconductor material differs from a second germanium concentration of the second semiconductor material.