System and method for generating random numbers based on non-volatile memory cell array entropy
View Patent ↗A memory device that generates a unique identifying number, and includes a plurality of memory cells and a controller. Each of the memory cells includes first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region. The controller is configured to apply one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions, measure the leakage currents, and generate a number based on the measured leakage currents.
1. A memory device, comprising:
a plurality of memory cells, wherein each of the memory cells includes:
first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions,
a floating gate disposed over and insulated from a first portion of the channel region, and
a select gate disposed over and insulated from a second portion of the channel region;
a controller configured to:
apply one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions,
measure the leakage currents, and
generate a number based on the measured leakage currents.
2. The device of claim 1 , wherein the controller is configured to generate at least part of the number by subtracting or comparing the measured leakage currents for a first pair of the memory cells from or to the measured leakage currents for a second pair of the memory cells.
3. The device of claim 1 , wherein a first pair of the memory cells are disposed adjacent to each other, and a second pair of the memory cells are disposed adjacent to each other, the device further comprising:
a first bit line connected to the second regions of the first pair of memory cells;
a second bit line connected to the second regions of the second pair of memory cells;
wherein the controller is configured to generate at least part of the number by subtracting or comparing leakage currents on the first bit line from or to leakage currents on the second bit line.
4. The device of claim 1 , wherein a first pair of the memory cells are disposed adjacent to each other, and a second pair of the memory cells are disposed adjacent to each other, the device further comprising:
a first bit line connected to the first regions of the first pair of memory cells;
a second bit line connected to the first regions of the second pair of memory cells;
wherein the controller is configured to generate at least part of the number by subtracting or comparing leakage currents on the first bit line from or to leakage currents on the second bit line.
5. The device of claim 1 , wherein each of the memory cells further comprises:
an erase gate disposed over and insulated from the first region.
6. The device of claim 4 , wherein each of the memory cells further comprises:
a control gate disposed over and insulated from the floating gate.
7. The device of claim 1 , wherein the controller is further configured to:
apply a positive voltage to the select gates while the memory cells are in a subthreshold state.
8. The device of claim 6 , wherein the controller is further configured to:
apply a positive voltage to the control gates while the memory cells are in a subthreshold state.
9. A memory device, comprising:
a plurality of pairs of memory cells, wherein each pair of the memory cells includes:
first, second and third regions formed in a semiconductor substrate, wherein a first channel region of the substrate extends between the first and second regions, and a second channel region of the substrate extends between the second and third regions,
a first floating gate disposed over and insulated from a first portion of the first channel region,
a second floating gate disposed over and insulated from a first portion of the second channel region,
a first select gate disposed over and insulated from a second portion of the first channel region, and
a second select gate disposed over and insulated from a second portion of the second channel region;
a controller configured to:
apply one or more positive voltages to the second regions, or to the first and third regions, of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the first and second channel regions,
measure the leakage currents, and
generate a number based on the measured leakage currents.
10. The device of claim 9 , further comprising:
a plurality of bit lines each connected to the first and third regions for one of the pairs of memory cells for receiving the leakage currents from the first and second channel regions for the one pair of the memory cells;
wherein the controller is configured to generate at least part of the number by subtracting or comparing leakage currents on one of the bit lines from or to leakage currents on another one of the bit lines.
11. The device of claim 10 , wherein for each of the bit lines, the leakage currents thereon are the leakage current from the first channel region and the leakage current from second channel region for the one pair of memory cells.
12. A method of identifying a memory device that includes a plurality of memory cells, wherein each of the memory cells includes:
first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions,
a floating gate disposed over and insulated from a first portion of the channel region, and
a select gate disposed over and insulated from a second portion of the channel region;
the method comprising:
applying one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions,
measuring the leakage currents, and
generating a number based on the measured leakage currents.
13. The method of claim 12 , wherein the generating of the number at least partially includes subtracting or comparing the measured leakage currents for a first pair of the memory cells from or to the measured leakage currents for a second pair of the memory cells.
14. The method of claim 12 , wherein:
a first pair of the memory cells are disposed adjacent to each other, and second pair of the memory cells are disposed adjacent to each other;
the device further comprises:
a first bit line connected to the second regions of the first pair of memory cells;
a second bit line connected to the second regions of the second pair of memory cells;
the generating of the number at least partially includes subtracting or comparing leakage currents on the first bit line from or to leakage currents on the second bit line.
15. The method of claim 12 , wherein:
a first pair of the memory cells are disposed adjacent to each other, and second pair of the memory cells are disposed adjacent to each other;
the device further comprises:
a first bit line connected to the first regions of the first pair of memory cells;
a second bit line connected to the first regions of the second pair of memory cells;
the generating of the number at least partially includes subtracting or comparing leakage currents on the first bit line from or to leakage currents on the second bit line.
16. The method of claim 12 , wherein each of the memory cells further comprises:
an erase gate disposed over and insulated from the first region.
17. The method of claim 16 , wherein each of the memory cells further comprises:
a control gate disposed over and insulated from the floating gate.
18. The method of claim 12 , further comprising:
applying a positive voltage to the select gates while the memory cells are in a subthreshold state.
19. The method of claim 17 , further comprising:
applying a positive voltage to the control gates while the memory cells are in a subthreshold state.
20. A method of identifying a memory device that includes a plurality of pairs of memory cells, wherein each pair of the memory cells includes:
first, second and third regions formed in a semiconductor substrate, wherein a first channel region of the substrate extends between the first and second regions, and a second channel region of the substrate extends between the second and third regions,
a first floating gate disposed over and insulated from a first portion of the first channel region,
a second floating gate disposed over and insulated from a first portion of the second channel region,
a first select gate disposed over and insulated from a second portion of the first channel region, and
a second select gate disposed over and insulated from a second portion of the second channel region;
the method comprising:
applying one or more positive voltages to the second regions, or to the first and third regions, of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the first and second channel regions,
measuring the leakage currents, and
generating a number based on the measured leakage currents.
21. The method of claim 20 , wherein:
the device further comprises a plurality of bit lines each connected to the first and third regions for one of the pairs of memory cells for receiving the leakage currents from the first and second channel regions for the one pair of the memory cells;
the generating of the number at least partially includes subtracting or comparing leakage currents on one of the bit lines from or to leakage currents on another one of the bit lines.
22. The method of claim 21 , wherein for each of the bit lines, the leakage currents thereon are the leakage current from the first channel region and the leakage current from second channel region for the one pair of memory cells.