Multi-tier memory device with rounded top part of joint structure and methods of making the same

1. A three-dimensional memory device, comprising:

a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate;

an inter-tier dielectric layer located over the first alternating stack;

a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer;

a memory stack structure vertically extending through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack, wherein the memory stack structure is located in a memory opening that extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack,

wherein:

the memory stack structure comprises a semiconductor channel and a memory film laterally surrounding the semiconductor channel;

the memory film comprises an upper portion embedded in the second alternating stack, a lower portion embedded in the first alternating stack, and an inter-tier level portion embedded in the inter-tier dielectric layer and laterally protrudes outward relative to outer sidewalls of the upper portion and the lower portion; and

the inter-tier level portion of the memory film has a convex upper surface that contacts a concave downward-facing surface of the inter-tier dielectric layer and the inter-tier level portion of the memory film that has the convex upper surface has a lateral extent in a range from 10 nm to 200 nm in a vertical cross-sectional view within a vertical plane that includes a vertical axis passing through a geometrical center of the memory opening.

2. The three-dimensional memory device of claim 1 , wherein:

the convex upper surface of the memory film azimuthally extends around the vertical axis passing through the geometrical center of the memory opening by 360 degrees.

3. The three-dimensional memory device of claim 1 , wherein an upper periphery of the convex upper surface adjoins a bottom periphery of a vertical or tapered outer sidewall of the upper portion of the memory film.

4. The three-dimensional memory device of claim 1 , wherein an upper periphery of the convex upper surface contacts a bottommost insulating layer within the second alternating stack.

5. The three-dimensional memory device of claim 1 , wherein the inter-tier dielectric layer comprises two different dielectric material compositions with a horizontal interface or a vertical interface therebetween.

6. The three-dimensional memory device of claim 1 , wherein:

the memory film comprises, from outside to inside, a blocking dielectric layer, a vertical stack of memory elements, and a tunneling dielectric layer; and

the convex upper surface of the memory films is a convex upper surface of the blocking dielectric layer.

7. The three-dimensional memory device of claim 6 , wherein:

the semiconductor channel includes a laterally protruding portion within the inter-tier level portion of the memory film;

a convex upper surface of the laterally protruding portion of the semiconductor channel contacts a concave downward-facing surface of the inter-tier level portion of the memory film; and

the vertical stack of memory elements is embodied as portions of a charge storage layer located at levels of the first and second electrically conductive layers; and

each of the blocking dielectric layer, the charge storage layer, and the tunneling dielectric layer has a respective uniform thickness throughout.

8. The three-dimensional memory device of claim 1 , wherein the inter-tier level portion of the memory film has a vertical cylindrical surface that adjoins a bottom periphery of the convex upper surface and contacting a vertical sidewall of the inter-tier dielectric layer.

9. The three-dimensional memory device of claim 1 , wherein the inter-tier level portion of the memory film has a planar annular bottom surface having an inner periphery that adjoins an upper periphery of an outer surface of the lower portion of the memory film.

10. The three-dimensional memory device of claim 1 , wherein the inter-tier level portion of the memory film has a convex lower surface contacting a concave upward-facing surface of the inter-tier dielectric layer.

11. The three-dimensional memory device of claim 1 , wherein each vertically neighboring pair of a first insulating layer and a first electrically conductive layer and each vertically neighboring pair of a second insulating layer and a second electrically conductive layer is spaced by a horizontal portion of a respective backside blocking dielectric layer that is adjoined to a cylindrical portion that laterally surrounds, and contacts an outer sidewall of, the memory film.

12. The three-dimensional memory device of claim 1 , wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

an integrated circuit comprising a driver circuit for monolithic three-dimensional NAND memory device is located on the substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings; and

the array of monolithic three-dimensional NAND strings comprises:

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

13. The three-dimensional memory device of claim 1 , wherein the inter-tier level portion of the memory film that has the convex upper surface has the lateral extent in the range from 20 nm to 100 nm in a vertical cross-sectional view within the vertical plane that includes the vertical axis passing through the geometrical center of the memory opening.

14. The three-dimensional memory device of claim 1 , wherein the concave downward-facing surface of the inter-tier dielectric layer has a lateral extent in the range from 10 nm to 200 nm in a vertical cross-sectional view within the vertical plane that includes the vertical axis passing through the geometrical center of the memory opening.

15. The three-dimensional memory device of claim 14 , wherein the concave downward-facing surface of the inter-tier dielectric layer has a lateral extent in the range from 20 nm to 100 nm in a vertical cross-sectional view within the vertical plane that includes the vertical axis passing through the geometrical center of the memory opening.