IP Library › Granted Patent US 12,289,886
Granted Patent B2
US 12,289,886 · App. 17/660,278 · Granted Apr 29, 2025

Multi-tier memory device with rounded joint structures and methods of making the same

Inventors: Nao Nagase (Yokkaichi, JP); Chiko Kudo (Yokkaichi, JP); Tsutomu Imai (Yokkaichi, JP)
Assignee: Sandisk Technologies, Inc.
H10B43/27H10B41/27
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Quick Facts
Patent No.
US 12,289,886
App. No.
17/660,278
Granted
Apr 29, 2025
Kind
B2
Abstract

A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.

Claims (69)

1. A method of forming a memory device, comprising:

forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate;

forming an inter-tier dielectric layer over the first alternating stack;

forming an etch mask layer including an opening therethrough over the inter-tier dielectric layer;

performing an isotropic etch process that isotropically recesses a material of the inter-tier dielectric layer from underneath the opening in the etch mask layer;

performing an anisotropic etch process after the isotropic etch process while the etch mask layer is present on the inter-tier dielectric layer to form a first-tier memory opening;

forming a sacrificial memory opening fill structure in the first-tier memory opening;

forming a second alternating stack of second insulating layers and second sacrificial material layers over the inter-tier dielectric layer;

forming a second-tier memory opening through the second alternating stack on a top surface of the sacrificial memory opening fill structure;

removing the sacrificial memory opening fill structure underneath the second-tier memory opening; and

forming a memory opening fill structure in volumes of the second-tier memory opening and the first-tier memory opening,

wherein the isotropic etch process forms a discrete cavity having a horizontal bottom surface and an annular concave surface adjoined to a periphery of the horizontal bottom surface.

2. The method of claim 1 , wherein an entirety of the annular concave surface has a uniform radius of curvature.

3. The method of claim 1 , wherein:

the anisotropic etch process forms a cylindrical cavity vertically extending through a lower portion of the inter-tier dielectric layer and the first alternating stack; and

the first-tier memory opening includes volumes of the cylindrical cavity and the discrete cavity.

4. The method of claim 1 , wherein the etch mask layer comprises a patterned photoresist layer including an array of discrete openings therethrough, wherein the opening in the etch mask layer is one of the discrete openings within the array of discrete openings.

5. The method of claim 1 , wherein the sacrificial memory opening fill structure is formed by:

depositing a sacrificial fill material in the first-tier memory opening and over the inter-tier dielectric layer; and

performing a planarization process that removes portions of the sacrificial fill material from above a horizontal plane including a top surface of the inter-tier dielectric layer.

6. The method of claim 5 , wherein:

the planarization process comprises a chemical mechanical polishing process; and

a top surface of the sacrificial memory opening fill structure is formed within the horizontal plane including the top surface of the inter-tier dielectric layer.

7. The method of claim 1 , wherein the second alternating stack is formed directly on a top surface of the inter-tier dielectric layer and directly on a top surface of the sacrificial memory opening fill structure.

8. The method of claim 1 , further comprising forming an additional inter-tier dielectric layer on a top surface of the inter-tier dielectric layer and the sacrificial memory opening fill structure.

9. The method of claim 8 , wherein:

the inter-tier dielectric layer comprises a first silicon oxide material;

the additional inter-tier dielectric layer comprises a second silicon oxide material;

a second isotropic etch process that etches a material of the additional inter-tier dielectric layer at a higher etch rate than the material of the inter-tier dielectric layer is performed after the first isotropic etch process; and

an etch rate of the second silicon oxide material during the second isotropic etch process is greater than an etch rate of the first silicon oxide material during the second isotropic etch process by a factor in a range from 2 to 1,000.

10. The method of claim 8 , wherein:

an upper portion of the sacrificial memory opening fill structure located above a horizontal plane including a topmost surface of the first alternating stack is removed by performing a first isotropic etch process that etches a material of the sacrificial memory opening fill structure selective to a material of the inter-tier dielectric layer;

a second isotropic etch process that etches a material of the additional inter-tier dielectric layer at a higher etch rate than the material of the inter-tier dielectric layer is performed after the first isotropic etch process; and

a third isotropic etch process that removes remaining portions of the sacrificial memory opening fill structure is performed after the second isotropic etch process.

11. The method of claim 1 , further comprising replacing the first sacrificial material layers and the second sacrificial material layers with first electrically conductive layers and second electrically conductive layers, respectively, after formation of the memory opening fill structure.

12. A method of forming a memory device, comprising:

forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate;

forming an inter-tier dielectric layer over the first alternating stack;

forming an etch mask layer including an opening therethrough over the inter-tier dielectric layer;

performing an isotropic etch process that isotropically recesses a material of the inter-tier dielectric layer from underneath the opening in the etch mask layer;

performing an anisotropic etch process after the isotropic etch process while the etch mask layer is present on the inter-tier dielectric layer to form a first-tier memory opening;

forming a sacrificial memory opening fill structure in the first-tier memory opening;

forming a second alternating stack of second insulating layers and second sacrificial material layers over the inter-tier dielectric layer;

forming a second-tier memory opening through the second alternating stack on a top surface of the sacrificial memory opening fill structure;

removing the sacrificial memory opening fill structure underneath the second-tier memory opening; and

forming a memory opening fill structure in volumes of the second-tier memory opening and the first-tier memory opening, wherein the isotropic etch process isotropically recesses the material of the inter-tier dielectric layer by a uniform recess distance that is less than a thickness of the inter-tier dielectric layer wherein the isotropic etch process forms a discrete cavity having a horizontal bottom surface and an annular concave surface adjoined to a periphery of the horizontal bottom surface.

13. The method of claim 12 , wherein the etch mask layer comprises a patterned photoresist layer including an array of discrete openings therethrough, wherein the opening in the etch mask layer is one of the discrete openings within the array of discrete openings.

14. The method of claim 12 , wherein the sacrificial memory opening fill structure is formed by:

depositing a sacrificial fill material in the first-tier memory opening and over the inter-tier dielectric layer; and

performing a planarization process that removes portions of the sacrificial fill material from above a horizontal plane including a top surface of the inter-tier dielectric layer.

15. The method of claim 12 , wherein the second alternating stack is formed directly on a top surface of the inter-tier dielectric layer and directly on a top surface of the sacrificial memory opening fill structure.

16. The method of claim 12 , further comprising replacing the first sacrificial material layers and the second sacrificial material layers with first electrically conductive layers and second electrically conductive layers, respectively, after formation of the memory opening fill structure.

17. A method of forming a memory device, comprising:

forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate;

forming an inter-tier dielectric layer over the first alternating stack;

forming an etch mask layer including an opening therethrough over the inter-tier dielectric layer;

performing an isotropic etch process that isotropically recesses a material of the inter-tier dielectric layer from underneath the opening in the etch mask layer;

performing an anisotropic etch process after the isotropic etch process while the etch mask layer is present on the inter-tier dielectric layer to form a first-tier memory opening;

forming a sacrificial memory opening fill structure in the first-tier memory opening;

forming an additional inter-tier dielectric layer on a top surface of the inter-tier dielectric layer and the sacrificial memory opening fill structure;

forming a second alternating stack of second insulating layers and second sacrificial material layers over the inter-tier dielectric layer;

forming a second-tier memory opening through the second alternating stack on a top surface of the sacrificial memory opening fill structure;

removing the sacrificial memory opening fill structure underneath the second-tier memory opening; and

forming a memory opening fill structure in volumes of the second-tier memory opening and the first-tier memory opening,

wherein:

an upper portion of the sacrificial memory opening fill structure located above a horizontal plane including a topmost surface of the first alternating stack is removed by performing a first isotropic etch process that etches a material of the sacrificial memory opening fill structure selective to a material of the inter-tier dielectric layer;

a second isotropic etch process that etches a material of the additional inter-tier dielectric layer at a higher etch rate than the material of the inter-tier dielectric layer is performed after the first isotropic etch process; and

a third isotropic etch process that removes remaining portions of the sacrificial memory opening fill structure is performed after the second isotropic etch process.

18. The method of claim 17 , further comprising replacing the first sacrificial material layers and the second sacrificial material layers with first electrically conductive layers and second electrically conductive layers, respectively, after formation of the memory opening fill structure.

Assignments (4)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2023
From: NAGASE, NAO; KUDO, CHIKO; IMAI, TSUTOMU
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 062355/0072 →
Continuity (1)
Related Publication 20230345720A1 · Oct 26, 2023
References Cited (74)
US 5915167A · Leedy · 1999 [cited by applicant]
US 8884357B2 · Wang et al. · 2014 [cited by applicant]
US 8946023B2 · Makala et al. · 2015 [cited by applicant]
US 9224752B1 · Lee et al. · 2015 [cited by applicant]
US 9230987B2 · Pachamuthu et al. · 2016 [cited by applicant]
US 9343358B1 · Xu · 2016 [cited by applicant]
US 9502471B1 · Lu et al. · 2016 [cited by applicant]
US 9570463B1 · Zhang et al. · 2017 [cited by applicant]
US 9627403B2 · Liu et al. · 2017 [cited by applicant]
US 9728551B1 · Lu et al. · 2017 [cited by applicant]
US 9768192B1 · Nakamura · 2017 [cited by applicant]
US 9780034B1 · Tsutsumi et al. · 2017 [cited by applicant]
US 9871052B2 · Lee · 2018 [cited by applicant]
US 9991280B2 · Nakamura et al. · 2018 [cited by applicant]
US 10056399B2 · Costa et al. · 2018 [cited by applicant]
US 10355012B2 · Shimabukuro et al. · 2019 [cited by applicant]
US 10381434B1 · Pachamuthu et al. · 2019 [cited by applicant]
US 10475879B1 · Pachamuthu et al. · 2019 [cited by applicant]
US 10600802B2 · Nakamura et al. · 2020 [cited by applicant]
US 10658377B2 · Kubo et al. · 2020 [cited by applicant]
US 10700089B1 · Hojo · 2020 [cited by examiner]
US 10748925B1 · Tsutsumi et al. · 2020 [cited by applicant]
US 10964715B2 · Kakazu et al. · 2021 [cited by applicant]
US 11296101B2 · Lee et al. · 2022 [cited by applicant]
US 20040042323A1 · Moshayedi · 2004 [cited by applicant]
US 20070259570A1 · Moshayedi · 2007 [cited by applicant]
US 20070296021A1 · Sugiyama et al. · 2007 [cited by applicant]
US 20110287612A1 · Lee et al. · 2011 [cited by applicant]
US 20120001247A1 · Alsmeier · 2012 [cited by applicant]
US 20120001252A1 · Alsmeier et al. · 2012 [cited by applicant]
US 20120003800A1 · Lee et al. · 2012 [cited by applicant]
US 20120198591A1 · Ohnesorge · 2012 [cited by applicant]
US 20130010558A1 · Chang et al. · 2013 [cited by applicant]
US 20130130468A1 · Higashitani et al. · 2013 [cited by applicant]
US 20140252454A1 · Rabkin et al. · 2014 [cited by applicant]
US 20140273373A1 · Makala et al. · 2014 [cited by applicant]
US 20150016242A1 · Ernstrom et al. · 2015 [cited by applicant]
US 20150155296A1 · Yoon · 2015 [cited by applicant]
US 20150294978A1 · Lu et al. · 2015 [cited by applicant]
US 20170062454A1 · Lu et al. · 2017 [cited by applicant]
US 20170229472A1 · Lu et al. · 2017 [cited by applicant]
US 20170236835A1 · Nakamura et al. · 2017 [cited by applicant]
US 20170243879A1 · Yu et al. · 2017 [cited by applicant]
US 20170271261A1 · Tsutsumi et al. · 2017 [cited by applicant]
US 20170271352A1 · Nakamura · 2017 [cited by applicant]
US 20170358593A1 · Yu et al. · 2017 [cited by applicant]
US 20180006049A1 · Inomata et al. · 2018 [cited by applicant]
US 20180182771A1 · Costa et al. · 2018 [cited by applicant]
US 20180331117A1 · Titus et al. · 2018 [cited by applicant]
US 20180374865A1 · Shimabukuro et al. · 2018 [cited by applicant]
US 20190280000A1 · Nakamura et al. · 2019 [cited by applicant]
US 20200006373A1 · Kubo et al. · 2020 [cited by applicant]
US 20200119038A1 · Hopkins et al. · 2020 [cited by applicant]
US 20200251486A1 · Tsutsumi et al. · 2020 [cited by applicant]
US 20200295040A1 · Tobioka · 2020 [cited by examiner]
US 20210159149A1 · Kitazawa · 2021 [cited by applicant]
US 20210249261A1 · Hopkins et al. · 2021 [cited by applicant]
US 20210305266A1 · Lee et al. · 2021 [cited by applicant]
US 20240371761A1 · Zhou et al. · 2024 [cited by applicant]
JP 2010161305 · 2010 [cited by applicant]
Endoh et al., “Novel Ultra High Density Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. [cited by applicant]
Hammond, M. L., “Silicon Epitaxy by Chemical Vapor Deposition,” pp. 45-106. [cited by applicant]
Csepregi, L. et al., “Substrate-Orientation Dependence of the Epitaxial Regrowth Rate from Si-Implanted Amorphous Si,” Journal of Applied Physics, vol. 49, No. 7, pp. 3906-3911 (1978). [cited by applicant]
Seidel, H. et al., “Anisotropic Etching of Crystalline Silicon in Alkaline Solutions,” J. Electrochem. Soc., vol. 137, No. 11, pp. 3612-3626, (1990). [cited by applicant]
Non-Final Office Communication for U.S. Appl. No. 15/071,575, dated Nov. 16, 2016, 13 pages. [cited by applicant]
Invitation to Pay Additional Fees from the International Searching Authority for International Patent Application No. PCT/US2017/017823, dated May 4, 2017, 18 pages. [cited by applicant]
International Application No. PCT/US2017/017823, International Search Report and Written Opinion, issued Jul. 5, 2017, 24pgs. [cited by applicant]
U.S. Appl. No. 17/166,357, filed Feb. 3, 2021, Sandisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/169,987, filed Feb. 8, 2021, Sandisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/189,153, filed Mar. 1, 2021, Sandisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/510,807, filed Oct. 26, 2021, Sandisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/715,662, filed Apr. 7, 2022, Sandisk Technologies LLC. [cited by applicant]
Imai, T. et al., “Multi-Tier Memory Device With Rounded Joint Structures And Methods Of Making The Same,” U.S. Appl. No. 17/660,265, filed Apr. 22, 2022. [cited by applicant]
USPTO Office Communication, Non-Final Office Action for U.S. Appl. No. 17/660,265, mailed Jan. 14, 2025, 25 pages. [cited by applicant]