Multi-tier three-dimensional memory device with stress compensation structures and method of making thereof

1. A semiconductor structure comprising:

a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, wherein the first-tier alternating stack comprises a first terrace region;

memory stack structures extending through the first-tier alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a memory film;

a first retro-stepped dielectric material portion comprising a compressive-stress-generating dielectric material, contacting stepped surfaces of the first terrace region, and laterally surrounding the first-tier alternating stack;

a patterned tensile-stress-generating material layer overlying the first retro-stepped dielectric material portion, laterally spaced outward from an outer periphery of a topmost layer within the first-tier alternating stack, and applying a tensile stress to the first retro-stepped dielectric material portion and to the first-tier alternating stack, wherein the patterned tensile-stress-generating material layer has continuous closed inner periphery that is defined by an opening therethrough; and

a dielectric material layer overlying the first-tier alternating stack, contacting the continuous closed inner periphery of the patterned tensile-stress-generating material layer, and applying a compressive stress to the first-tier alternating stack and to the patterned tensile-stress-generating material layer.

2. The semiconductor structure of claim 1 , wherein:

the patterned tensile-stress-generating material layer comprises a silicon nitride layer;

the dielectric material layer comprises a silicon oxide or silicon oxynitride layer; and

a nitrogen concentration gradient is present near an interface between the patterned tensile-stress-generating material layer and the dielectric material layer such that nitrogen concentration in the dielectric material layer decreases with distance from the interface.

3. The semiconductor structure of claim 1 , wherein:

the patterned tensile-stress-generating material layer comprises a first silicon nitride layer having a first atomic concentration of hydrogen; and

the dielectric material layer comprises a second silicon nitride layer having second atomic concentration of hydrogen which is higher than the first atomic concentration of hydrogen.

4. The semiconductor structure of claim 1 , wherein the patterned tensile-stress-generating material layer and the dielectric material layer have different thicknesses.

5. The semiconductor structure of claim 1 , wherein a topmost surface of the first retro-stepped dielectric material portion contacts a bottom surface of the patterned tensile-stress-generating material layer.

6. The semiconductor structure of claim 1 , wherein the first retro-stepped dielectric material portion contacts an entire set of sidewalls of an inner periphery of the patterned tensile-stress-generating material layer.

7. The semiconductor structure of claim 1 , wherein an interface between the first retro-stepped dielectric material portion and the patterned tensile-stress-generating material layer has a taper angle in a range from 15 degrees and 85 degrees with respect to a vertical direction.

8. The semiconductor structure of claim 1 , wherein the patterned tensile-stress-generating material layer comprises a tungsten layer, and further comprising contact via structures extending through the patterned tensile-stress-generating material layer and the first retro-stepped dielectric material portion and contacting a top surface of a respective one of the first electrically conductive layers, wherein each of the contact via structures is electrically isolated from the patterned tensile-stress-generating material layer by a respective cylindrical dielectric liner.

9. A semiconductor structure comprising:

a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, wherein the first-tier alternating stack comprises a first terrace region;

memory stack structures extending through the first-tier alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a memory film;

a first retro-stepped dielectric material portion comprising a compressive-stress-generating dielectric material, contacting stepped surfaces of the first terrace region, and laterally surrounding the first-tier alternating stack; and

a patterned tensile-stress-generating material layer overlying the first retro-stepped dielectric material portion, laterally spaced outward from an outer periphery of a topmost layer with the first-tier alternating stack, and applying a tensile stress to the first retro-stepped dielectric material portion and to the first-tier alternating stack;

a second-tier alternating stack of the second insulating layers and second electrically conductive layers overlying the first-tier alternating stack, wherein each of the memory stack structures extends through the second-tier alternating stack and an additional vertical stack of memory elements located at levels of a predominant subset of the second electrically conductive layers;

wherein:

the semiconductor structure comprises a monolithic three-dimensional NAND memory device;

the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains a peripheral device region comprising an integrated circuit comprising a driver circuit for the memory device located thereon;

word line contact via structures are located in a word line contact via region, extend through the patterned tensile-stress-generating material layer and the first retro-stepped dielectric material portion and contact a top surface of the respective the word line; and

a patterned tensile-stress-generating material layer is located over the peripheral device region and over an outer portion of the word line contact via region, but not over an inner portion of the word line contact via region and not over a memory array region comprising a memory plane which contains the array of monolithic three-dimensional NAND strings.