Three-dimensional memory device containing annular etch-stop spacer and method of making thereof
A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.
1. A monolithic three-dimensional memory device, comprising:
a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate;
an insulating cap layer overlying the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer;
memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack;
memory stack structures located within the memory openings, wherein each of the memory stack structures comprises a semiconductor channel and a memory film; and
annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures,
wherein:
outer sidewalls of the annular spacers are vertical;
inner sidewalls of the annular spacers comprise lower vertical portions and upper tapered portions; and
the upper tapered portions contact tapered bottom surfaces of the memory films of the memory stack structures.
2. A monolithic three-dimensional memory device, comprising:
a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate;
an insulating cap layer overlying the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer;
memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack;
memory stack structures located within the memory openings, wherein each of the memory stack structures comprises a semiconductor channel and a memory film;
annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures; and
a dielectric etch stop layer contacting bottom surfaces of the annular spacers and comprising a dielectric material that is different in composition from the first and second insulating layers.
3. The monolithic three-dimensional memory device of claim 2 , wherein:
the first and second insulating layers comprise silicon oxide; and
the annular spacers and the dielectric etch stop layer comprise silicon nitride.
4. The monolithic three-dimensional memory device of claim 2 , wherein:
the insulating cap layer comprises a first insulating cap layer and a second insulating cap layer contacting a top surface of the first insulating cap layer; and
the second insulating cap layer includes downward-protruding portions that contact sidewalls of the dielectric etch stop layer.
5. The monolithic three-dimensional memory device of claim 4 , wherein:
the first insulating cap layer contacts outer sidewalls of the annular spacers; and
the second insulating cap layer contacts tapered portions of inner sidewalls of the annular spacers.
6. The monolithic three-dimensional memory device of claim 4 , further comprising:
a first retro-stepped dielectric material portion overlying first stepped surfaces of the first alternating stack;
a second retro-stepped dielectric material portion overlying second stepped surfaces of the second alternating stack; and
word line contact via structures extending at least through the second retro-stepped dielectric material portion and contacting top surfaces of a respective one of the first and second electrically conductive layers,
wherein the second insulating cap layer is disposed between the first retro-stepped dielectric material portion and the second dielectric material portion.
7. The monolithic three-dimensional memory device of claim 2 , further comprising:
backside trenches vertically extending through the second alternating stack, the insulating cap layer, and the first alternating stack; and
insulating material portions located in the backside trenches and contacting sidewalls of the backside trenches and laterally spaced from the dielectric etch stop layer.
8. The monolithic three-dimensional memory device of claim 7 , further comprising:
backside contact via structures located within a respective one of the insulating material portions in the backside trenches; and
source regions located in the substrate and contacting a bottom surface of a respective one of the backside contact via structures.
9. A monolithic three-dimensional memory device, comprising:
a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate;
an insulating cap layer overlying the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer;
memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack;
memory stack structures located within the memory openings, wherein each of the memory stack structures comprises a semiconductor channel and a memory film; and
annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures,
wherein each of the memory stack structures has a laterally bulging portion that is located within the insulating cap layer and overlying a respective one of the annular spacers, wherein top surfaces of the laterally bulging portions are within a horizontal plane including a top surface of the insulating cap layer.
10. A monolithic three-dimensional memory device, comprising:
a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate;
an insulating cap layer overlying the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer;
memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack;
memory stack structures located within the memory openings, wherein each of the memory stack structures comprises a semiconductor channel and a memory film; and
annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures,
wherein:
the monolithic three-dimensional memory structure comprises a monolithic three-dimensional NAND memory device;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.