Vertical field effect transistor with self-aligned backside trench epitaxy
A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source/drain region of a field effect transistor. The bottom source/drain region includes a trench epitaxy later located underneath a bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source/drain region by a bottom spacer. A top source/drain region is located above a topmost surface of the channel fin. The top source/drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure further includes a backside metal contact within a backside interlayer dielectric. The backside metal contact is electrically connected to, and vertically aligned with, the bottom source/drain region.
1 . A semiconductor structure, comprising:
a field effect transistor including
a channel fin extending vertically from a bottom source/drain region, the bottom source/drain region including a trench epitaxy layer located vertically underneath and in direct contact with a bottommost surface of the channel fin,
a high-k metal gate stack disposed along sidewalls of the channel fin, the high-k metal gate being separated from the bottom source/drain region by a bottom spacer, and
a top source/drain region located above a topmost surface of the channel fin, the top source/drain region being separated from the high-k metal gate by a top spacer;
a front-end-of-line level, the front-end-of-line level being electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level, wherein the field effect transistor is a vertical field effect transistor;
a backside interlayer dielectric surrounding the bottom source/drain region and located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level; and
a backside metal contact within the backside interlayer dielectric, the backside metal contact electrically connected to, and vertically aligned with, the bottom source/drain region, partially surrounding the bottom source/drain region, and partially wrapped around a portion of the trench epitaxy layer.
2 . The semiconductor structure of claim 1 , further comprising:
a metal contact within an interlevel dielectric, the metal contact being in electric contact with an uppermost surface of the top source/drain region.
3 . The semiconductor structure of claim 1 , wherein the backside metal contact fills an area located between two adjacent bottom source/drain regions partially surrounding a portion of the two adjacent bottom source/drain regions.
4 . The semiconductor structure of claim 1 , further comprising:
a backside interconnect structure electrically connected to the backside metal contact.
5 . The semiconductor structure of claim 2 , further comprising:
a carrier wafer in contact with a surface of the back-end-of-line interconnect level opposing the top source/drain region and the metal contact.
6 . The semiconductor structure of claim 1 , wherein the backside metal contact is composed of a conductive material selected from the group consisting of Ru, Cu, Co, W, and Al.
7 . The semiconductor structure of claim 1 , wherein a first side of the trench epitaxy layer is in direct contact with the channel fin, and a second side of the trench epitaxy layer, opposing the first side of the trench epitaxy layer, is in direct contact with the backside metal contact.
8 . The semiconductor structure of claim 1 , wherein the trench epitaxy layer includes similar materials and a same dopant concentration as the top source/drain region.
9 . A method of forming a semiconductor structure, comprising:
forming a channel fin extending vertically from a bottom source/drain region of a field effect transistor, the bottom source/drain region including a trench epitaxy layer located vertically underneath and in direct contact with a bottommost surface of the channel fin;
forming a high-k metal gate stack disposed along sidewalls of the channel fin, the high-k metal gate being separated from the bottom source/drain region by a bottom spacer;
forming a top source/drain region located above a topmost surface of the channel fin, the top source/drain region being separated from the high-k metal gate by a top spacer;
forming a front-end-of-line level including the field effect transistor, the front-end-of-line level being electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level, wherein the field effect transistor is a vertical field effect transistor;
forming a backside interlayer dielectric surrounding the bottom source/drain region and located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level; and
forming a backside metal contact within the backside interlayer dielectric, the backside metal contact electrically connected to, and vertically aligned with, the bottom source/drain region, partially surrounding the bottom source/drain region, and partially wrapped around a portion of the trench epitaxy layer.
10 . The method of claim 9 , further comprising:
forming a metal contact within an interlevel dielectric, the metal contact being in electric contact with an uppermost surface of the top source/drain region.
11 . The method of claim 9 , wherein the backside metal contact fills an area located between two adjacent bottom source/drain regions partially surrounding a portion of the two adjacent bottom source/drain regions.
12 . The method of claim 9 , further comprising:
forming a backside interconnect structure electrically connected to the backside metal contact.
13 . The method of claim 10 , further comprising:
forming a carrier wafer in contact with a surface of the back-end-of-line interconnect level opposing the top source/drain region and the metal contact.
14 . The method of claim 9 , wherein the backside metal contact is composed of a conductive material selected from the group consisting of Ru, Cu, Co, W, and Al.
15 . The method of claim 9 , wherein a first side of the trench epitaxy layer is in direct contact with the channel fin and a second side of the trench epitaxy layer, opposing the first side of the trench epitaxy layer, is in direct contact with the backside metal contact.
16 . The method of claim 9 , wherein the trench epitaxy layer is epitaxially grown using a low-temperature epitaxial process, and wherein the trench epitaxy layer includes similar materials and a same dopant concentration as the top source/drain region.