IP Library › Granted Patent US 10,381,434
Granted Patent B1
US 10,381,434 · App. 16/021,831 · Granted Aug 13, 2019

Support pillar structures for leakage reduction in a three-dimensional memory device

Inventors: Jayavel Pachamuthu (San Jose, CA); Hiroyuki Kinoshita (San Jose, CA); Yao-Sheng Lee (Tampa, FL)
Assignee: SANDISK TECHNOLOGIES LLC
H01L29/0607G11C16/0408G11C16/0466H01L27/11556H01L27/11582
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Quick Facts
Patent No.
US 10,381,434
App. No.
16/021,831
Granted
Aug 13, 2019
Kind
B1
Abstract

Multiple tier structures including a respective alternating stack of insulating layers and electrically conductive layers is formed over a substrate. A memory opening fill structure extends through the alternating stacks, and includes a vertical semiconductor channel and a memory film. A support pillar structure extends through at least an upper alternating stack, and includes a dummy memory film and a dummy memory film. The support pillar structure may be narrower than the memory opening fill structure at a bottommost layer of the upper alternating stack. Additionally or alternatively, the dummy memory film may be located above a horizontal plane including a topmost surface of a lower alternating stack. Optionally, another support pillar structure including a dielectric material may be provided underneath the support pillar structure in the lower alternating stack. A dielectric material can be provided at levels of the lower alternating stack in a support pillar structure to reduce inter-level leakage current.

Claims (18)

1. A three-dimensional memory device, comprising:

a first-tier structure located over a top surface of a substrate, wherein the first-tier structure comprises a first alternating stack of first insulating layers and first electrically conductive layers and a first retro-stepped dielectric material portion overlying first stepped surfaces of the first alternating stack;

a second-tier structure overlying the first-tier structure, wherein the second-tier structure comprises a second alternating stack of second insulating layers and second electrically conductive layers and a second retro-stepped dielectric material portion overlying second stepped surfaces of the second alternating stack;

a memory opening fill structure extending through all layers within the second alternating stack and the first alternating stack, wherein the memory opening fill structure comprises a vertical semiconductor channel and a memory film that extend through the second alternating stack and a subset of layers within the first alternating stack; and

a support pillar structure extending through all layers within the second alternating stack and including a dummy semiconductor channel having a same material composition as the semiconductor channel and including a dummy memory film having a same material composition as the memory film, wherein a bottommost surface of the dummy memory film is located above a horizontal plane including a topmost surface of the first alternating stack.

2. The three-dimensional memory device of claim 1 , wherein the support pillar structure extends through the subset of layers within the first alternating stack.

3. The three-dimensional memory device of claim 2 , wherein the support pillar structure comprises a doped semiconductor material portion contacting a bottom surface of the dummy memory film.

4. The three-dimensional memory device of claim 3 , further comprising an inter-tier dielectric material layer overlying the first-tier structure and underlying the second-tier structure and laterally surrounding, and contacting, the doped semiconductor material portion.

5. The three-dimensional memory device of claim 2 , wherein the support pillar structure comprises at least one dielectric material portion that contacts sidewalls of the subset of layers within the first alternating stack.

6. The three-dimensional memory device of claim 5 , wherein the at least one dielectric material portion laterally surrounds a semiconductor material portion vertically extending through a plurality of first insulating layers and including electrical dopants at a dopant concentration less than 1.0×10 17 /cm 3 .

7. The three-dimensional memory device of claim 6 , wherein the at least one dielectric material portion comprises a conformal dielectric liner having a uniform thickness and continuously extending over the sidewalls of the plurality of first insulating layers.

8. The three-dimensional memory device of claim 6 , wherein the at least one dielectric material portion comprises a plurality of annular dielectric spacers comprising a dielectric oxide of a semiconductor material of the semiconductor material portion.

9. The three-dimensional memory device of claim 6 , further comprising a doped semiconductor material portion contacting a bottom surface of the dummy memory film and contacting a top surface of the semiconductor material portion and including electrical dopants at a dopant concentration in a range from 5.0×10 19 /cm 3 and 2.0×10 21 /cm 3 .

10. The three-dimensional memory device of claim 5 , wherein the at least one dielectric material portion comprises a dielectric pillar structure contacting a bottom surface and a sidewall of the dummy memory film and extending through, and contacting sidewalls of, a plurality of first insulating layers within the first alternating stack.

11. The three-dimensional memory device of claim 1 , further comprising a first-tier support pillar structure underlying the support pillar structure, extending through the first alternating stack, having a partial areal overlap with the support pillar structure in a plan view, and not in direct contact with the support pillar structure.

12. The three-dimensional memory device of claim 1 , wherein:

the memory film comprises a first layer stack including a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer; and

the dummy memory film comprises a second layer stack including a dummy tunneling dielectric layer having a same thickness and a same composition as the tunneling dielectric layer, a dummy charge storage layer having a same thickness and a same composition as the charge storage layer, and a dummy blocking dielectric layer having a same thickness and a same composition as the blocking dielectric layer.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2018
From: PACHAMUTHU, JAYAVEL; KINOSHITA, HIROYUKI; LEE, YAO-SHENG
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 046425/0626 →
Cited By (12)
US 12,213,320 US 12,230,573 US 12,256,548 US 12,289,886 US 12,302,571 US 12,310,020 US 12,322,710 US 12,324,150 US 12,349,352 US 12,438,100 US 12,557,278 US 12,713,611