Nonvolatile semiconductor memory device and method for manufacturing same
A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
1. A nonvolatile semiconductor memory device, comprising:
a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction;
a selection gate electrode stacked on the stacked structural unit in the first direction;
an insulating layer stacked on the selection gate electrode in the first direction;
a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction;
a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and
a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit, wherein at least a portion of a source-drain diffusion region opposing to the selection gate electrode in a direction perpendicular to the first direction,
wherein the source-drain diffusion region includes phosphorus or boron as an impurity,
wherein the source-drain diffusion region is provided at a position proximal to an upper end of the selection gate electrode, and
a lower end of the source-drain diffusion region is positioned below the upper end of the selection gate electrode.
2. The device according to claim 1 , wherein an upper end of the first core unit is disposed between an upper end and a lower end of the selection gate electrode on the upper end side of the selection gate electrode, and a lower end of the first conducting layer faces the selection gate electrode.
3. The device according to claim 1 , wherein the first semiconductor pillar includes at least one selected from polysilicon and amorphous silicon.
4. The device according to claim 3 , wherein the insulating layer includes silicon oxide.
5. The device according to claim 4 , wherein the first core unit includes silicon nitride.
6. A nonvolatile semiconductor memory device, comprising:
a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction;
a selection gate electrode stacked on the stacked structural unit in the first direction;
an insulating layer stacked on the selection gate electrode in the first direction;
a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction, the first semiconductor pillar including a source-drain diffusion region;
a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and
a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit, wherein
a position of a lower end of the source-drain diffusion region in the first direction is below a position of an upper end of the selection gate electrode in the first direction,
the source-drain diffusion region is provided at a position proximal to an upper end of the selection gate electrode, and
a lower end of the source-drain diffusion region is positioned below the upper end of the selection gate electrode.
7. The device according to claim 6 , wherein the first conducting layer includes polysilicon and an impurity added to the polysilicon.
8. The device according to claim 7 , wherein the first semiconductor pillar includes at least one selected from polysilicon and amorphous silicon.
9. The device according to claim 8 , wherein the insulating layer includes silicon oxide.
10. The device according to claim 9 , wherein the first core unit includes silicon nitride.