Semiconductor device including control switches to reduce pin capacitance
A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.
1. A semiconductor device, comprising:
a plurality of semiconductor stacked die, each semiconductor die of the plurality of semiconductor die comprising a plurality of die bond pads; and
a substrate, comprising:
a plurality of contact pads, one contact pad for each of the plurality of die bond pads from each of the plurality of semiconductor die; and
a plurality of control switches in the substrate, the plurality of control switches comprising:
a first group of control switches electrically connected to a first semiconductor die of the plurality of semiconductor die, each of the control switches in the first group physically connected to a contact pad of the plurality of contact pads, and electrically connected to a die bond pad of the plurality of die bond pads of the first semiconductor die,
a first control trace associated with the first group of control switches such that each control switch in the first group of control switches is either open or closed, depending upon whether a first voltage passes through the first control trace, and signal transfer to/from the first semiconductor die is blocked when the first group of control switches are open,
a second group of control switches electrically connected to a second semiconductor die of the plurality of semiconductor die, each of the control switches in the second group physically connected to a contact pad of the plurality of contact pads, and electrically connected to a die bond pad of the plurality of die bond pads of the second semiconductor die, and
a second control trace associated with the second group of control switches such that each control switch in the second group of control switches is either open or closed, depending upon whether a second voltage passes through the second control trace, and signal transfer to/from the second semiconductor die is blocked when the second group of control switches are open.
2. The semiconductor device of claim 1 , wherein the plurality of control switches are micro-electromechanical control switches.
3. The semiconductor device of claim 1 , wherein the plurality of control switches are integrated circuit control switches.
4. The semiconductor device of claim 1 , wherein the plurality of control switches are open in the absence of the first and second voltages through the first and second control traces, the first voltage through the first control trace closes the first group of control switches.
5. The semiconductor device of claim 1 , further comprising the substrate, the plurality of semiconductor die supported on the substrate, the substrate comprising the plurality of contact pads, the plurality of control switches comprising micro-electromechanical switches on the substrate.
6. The semiconductor device of claim 5 , further comprising a plurality of wire bonds, each wire bond of the plurality of wire bonds extending between a contact pad of the plurality of contact pads and a respective die bond pad on a respective semiconductor die.
7. The semiconductor device of claim 5 , wherein each of the plurality of contact pads has an associated control switch of the plurality of control switches.
8. The semiconductor device of claim 5 , the plurality of contact pads comprising a first row of contact pads associated with the first group of control switches, the first group of control switches arranged in a second row, and the plurality of contact pads comprising a third row of contact pads associated with the second group of control switches, the second group of control switches arranged in a fourth row.
9. The semiconductor device of claim 8 , the second row further comprising the first control trace, and the fourth row further comprising the second control trace.
10. The semiconductor device of claim 1 , wherein the plurality of semiconductor die are flash memory die.
11. A semiconductor device, comprising:
a substrate comprising a plurality of contact pads, the plurality of contact pads comprising a first group of contact pads and a second group of contact pads;
a plurality of semiconductor die stacked on the substrate, a first semiconductor die electrically coupled to the first group of contact pads and a second semiconductor die electrically coupled to the second group of contact pads;
a plurality of control switches fabricated in the substrate, the plurality of control switches comprising a first group of control switches, each contact pad of the first group of contact pads being physically connected to a single control switch from the first group of control switches, and a second group of control switches, each contact pad of the second group of contact pads being physically connected to a single control switch from the second group of control switches; and
a plurality of control traces, the plurality of control traces comprising a first control trace on the substrate associated with the first group of control switches and a second control trace on the substrate associated with the second group of control switches.
12. The semiconductor device of claim 11 , wherein the plurality of control switches are micro-electromechanical control switches.
13. The semiconductor device of claim 11 , wherein the first control trace is configured to open or close the first group of control switches depending on a first voltage through the first control trace.
14. The semiconductor device of claim 13 , wherein each control switch of the first group of control switches includes a cantilevered portion moving between a first position where the first group of control switches is open, and a second position where the first group of control switches is closed, the cantilevered portion moving between the first and second positions based on whether the first voltage is applied to the first control trace.
15. The semiconductor device of claim 11 , further comprising a plurality of wire bonds, each wire bond of the plurality of wire bonds extending between a contact pad of the plurality of contact pads and a respective die bond pad on a respective semiconductor die.
16. A semiconductor device operating under control of a controller die, comprising:
a substrate comprising a plurality of contact pads, the plurality of contact pads comprising a first group of contact pads and a second group of contact pads;
a plurality of semiconductor die stacked on the substrate, the plurality of semiconductor die comprising:
a first semiconductor die comprising a first plurality of die bond pads, one die bond pad in the first plurality of die bond pads for each of the contact pads in the first group of contact pads, and
a second semiconductor die comprising a second plurality of die bond pads, one die bond pad in the second plurality of die bond pads for each of the contact pads in the second group of contact pads;
a plurality of wire bonds, a first group of wire bonds electrically coupling the first plurality of die bond pads of the first semiconductor die to the first group of contact pads and a second group of wire bonds electrically coupling the second plurality of die bond pads of the second semiconductor die to the second group of contact pads;
a plurality of control switches in the substrate, the plurality of control switches comprising a first group of control switches attached to the first group of contact pads such that each contact pad of the first group of contact pads is physically connected to a single control switch from the first group of control switches, and a second group of control switches attached to the second group of contact pads such that each contact pad of the second group of contact pads is physically connected to a single control switch from the second group of control switches; and
a plurality of control traces, the plurality of control traces comprising a first control trace on the substrate associated with the first group of control switches and a second control trace associated with the second group of control switches, the first and second control traces configured to receive a chip enable signal from the controller die at different times, receipt of the chip enable signal in the first control trace closing the first group of control switches and enabling the first semiconductor die while the second group of control switches remain open, blocking signal transfer to/from the second semiconductor die.
17. The semiconductor device of claim 16 , wherein all wire bonds of the plurality of wire bonds are between a die bond pad of a semiconductor die and a contact pad on the substrate.
18. The semiconductor device of claim 16 , wherein the plurality of contact pads comprise at least as many contact pads as there are die bond pads associated with the wire bonds.
19. The semiconductor device of claim 16 , wherein the plurality of control switches comprise at least as many control switches as there are die bond pads associated with the wire bonds.