Granted Patent B2

US 10,516,333 · App. 15/916,421 · Granted Dec 24, 2019

Abstract

Claims (58)

1. A circuit for slew rate control for a high-side switch, the circuit comprising:

a sample and level-shift circuit, the sample and level-shift circuit connected to the high-side switch;

a charge-limiting circuit; and

a sampling capacitor configured to:

sample an input voltage corresponding to the sample and level-shift circuit; and

charge a gate capacitance of the high-side switch; and

wherein the charge-limiting circuit:

includes a current sink configured to limit charge;

includes a transistor connected parallel with the current sink, the transistor configured to remove any charge limitation corresponding to the current sink; and

is configured to limit a rate of charge transferred to the gate capacitance of the high-side switch per unit of time;

wherein the sample and level-shift circuit is a bootstrap circuit connected to a source of the high-side switch.

2. The circuit of claim 1 , wherein the charge-limiting circuit is further configured to limit a current corresponding to the sampling capacitor.

3. The circuit of claim 1 , wherein the charge-limiting circuit is further configured to limit a voltage corresponding to the sampling capacitor.

4. The circuit of claim 1 , wherein the charge-limiting circuit is further configured to limit a sampling capacitance corresponding to the sample and level-shift circuit.

5. The circuit of claim 1 , wherein the charge-limiting circuit is further configured to limit a frequency corresponding to the sample and level-shift circuit.

6. The circuit of claim 1 , wherein the high-side switch is an n-channel metal-oxide semiconductor field-effect transistor (nMOS transistor).

7. The circuit of claim 1 , wherein the slew rate control circuit for the high-side switch is an integrated circuit on a single chip.

8. The circuit of claim 1 , wherein the charge-limiting circuit includes an adjustable voltage supply.

9. The circuit of claim 1 , wherein the charge-limiting circuit includes the sampling capacitor.

10. The circuit of claim 1 , wherein:

the sampling capacitor is an adjustable sampling capacitor; and

the charge-limiting circuit includes the sampling capacitor.

11. The circuit of claim 1 , wherein:

the high-side switch is an n-channel metal-oxide semiconductor field-effect transistor (NMOSFET) connected to a power supply at a drain of the NMOSFET;

the power supply is configured to provide a voltage at least as great as the input voltage; and

the NMOSFET is configured to be switched on when the power supply provides the voltage at least as great as the input voltage.

12. The circuit of claim 1 , wherein:

the input voltage is sampled at a first side of the sampling capacitor;

the charge-limiting circuit is connected between a second side of the sampling capacitor and ground; and

the first side of the sampling capacitor is on an opposite side of the sampling capacitor as compared to the second side of the sample capacitor.

13. The circuit of claim 1 , wherein the bootstrap circuit connected to the source of the high-side switch includes a connection between a bottom plate of the sampling capacitor and the source of the high-side switch.

14. The circuit of claim 1 , wherein the sample and-level circuit is configured to dynamically adjust a voltage of a gate of the high-side switch based upon output of the high-side switch.

15. A method for controlling a slew rate of a high-side switch, the method comprising:

supplying an input current to a sample and level-shift circuit;

sampling an input voltage with a sampling capacitor configured for the sampling of the input voltage;

level-shifting the input voltage;

charging a gate capacitance of the high-side switch using the sampling capacitor; and

limiting a charge supplied to the sampling capacitor, the charge limited by at least one current sink;

connecting a bootstrap circuit to a source of the high-side switch; and

connecting a transistor in parallel with the at least one current sink, and turning on the transistor to remove any charge limitation corresponding to the at least one current sink.

16. The method of claim 15 , further comprising selecting one of the at least one current sink, each of the at least one current sink corresponding to a different high-side switch slew rate.

17. The method of claim 15 , further comprising limiting a current corresponding to the sampling capacitor.

18. The method of claim 15 , further comprising limiting a voltage corresponding to the sampling capacitor.

19. The method of claim 15 , further comprising limiting a sampling capacitance corresponding to the sample and level-shift circuit.

20. The method of claim 15 , further comprising limiting a frequency corresponding to the sample and level-shift circuit.

21. A switch apparatus, comprising:

a high-side switch; and

a control circuit for slew rate control for a high-side switch, the control circuit comprising:

a sample and level-shift circuit, the sample and level-shift circuit connected to the high-side switch;

a charge-limiting circuit; and

a sampling capacitor configured to:

sample an input voltage corresponding to the sample and level-shift circuit; and

charge a gate capacitance of the high-side switch; and

wherein:

the charge-limiting circuit configured to limit a rate of charge transferred to the gate capacitance of the high-side switch per unit of time, including:

a current sink configured to limit charge;

a transistor connected parallel with the current sink, the transistor configured to remove any charge limitation corresponding to the current sink; and

the sample and level-shift circuit is a bootstrap circuit connected to a source of the high-side switch.

Assignments (13)