3D integrated circuit device
A 3D integrated circuit device, the device including: a first level including a single crystal wafer, the first level includes a plurality of first transistors; a second level overlaying the first level, the second level includes a plurality of second transistors; a third level overlaying the second level, the third level includes a plurality of third transistors; a first metal layer interconnecting the plurality of first transistors; a second metal layer overlaying the third level, where the second level has a first coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first metal layer, where the connection path includes at least one through-layer via, where the through-layer via includes a material, the material has a second co-efficient of thermal expansion, and where the second co-efficient of thermal expansion is within 50 percent of the first coefficient of thermal expansion.
1. A 3D integrated circuit device, the device comprising:
a first level comprising a single crystal wafer, said first level comprises a plurality of first transistors;
a second level overlaying said first level, said second level comprises a plurality of second transistors;
a third level overlaying said second level, said third level comprises a plurality of third transistors;
a first metal layer interconnecting said plurality of first transistors;
a second metal layer overlaying said third level,
wherein said second level has a first coefficient of thermal expansion; and
a connection path connecting at least one of said plurality of second transistors to said first metal layer,
wherein said connection path comprises at least one through-layer via,
wherein said through-layer via comprises a material, said material has a second co-efficient of thermal expansion,
wherein said second co-efficient of thermal expansion is within 50 percent of said first coefficient of thermal expansion,
wherein at least one of said plurality of first transistors, at least one of said plurality of second transistors and at least one of said plurality of third transistors are aligned to each other with less than 100 nm misalignment,
wherein at least one of said second transistors is at least partially overlaying at least one of said first transistors,
wherein supply of ground or power to at least one of said second transistors is controlled by at least one of said first transistors,
wherein at least one of said second transistors is self-aligned to at least one of said third transistors, and
wherein at least one of said second transistors is a junction-less transistor.
2. The device according to claim 1 , further comprising:
a third memory cell comprising at least one of said plurality of third transistors;
a second memory cell comprising at least one of said plurality of second transistors; and
a memory periphery circuit comprising at least one of said plurality of first transistors,
wherein said memory periphery circuit controls said third memory cell and second memory cell.
3. The device according to claim 1 ,
wherein at least one of said plurality of second transistors is connected to at least one of said plurality of third transistors with an ohmic connection.
4. The device according to claim 1 ,
wherein said at least one through-layer vias is formed through and in direct contact with a source or drain of at least one of said plurality of second transistors.
5. The device according to claim 1 ,
wherein said plurality of second transistors comprise a second gate dielectric;
wherein said plurality of third transistors comprise a third gate dielectric, and
wherein said second gate dielectric and said third gate dielectric are part of the same layer.
6. The device according to claim 1 ,
wherein at least one of said plurality of third transistors is controlled by a third control line,
wherein at least one of said plurality of second transistors is controlled by a second control line, and
wherein a control circuit controlling said second control line and third control line comprises a portion of said plurality of first transistors.
7. The device according to claim 1 ,
wherein at least one of said plurality of third transistors comprises polysilicon.
8. A 3D integrated circuit device, the device comprising:
a first level comprising a single crystal wafer, said first level comprises a plurality of first transistors;
a second level overlaying said first level, said second level comprises a plurality of second transistors;
a third level overlaying said second level, said third level comprises a plurality of third transistors;
a first metal layer interconnecting said plurality of said first transistors;
a second metal layer overlaying said third level,
wherein said second level has a first coefficient of thermal expansion; and
a connection path connecting at least one of said plurality of second transistors to said first metal layer,
wherein said connection path comprises at least one through-layer via,
wherein said through-layer via comprises a material, said material has a second co-efficient of thermal expansion,
wherein said second co-efficient of thermal expansion is within 50 percent of said first coefficient of thermal expansion,
wherein at least one of said plurality of first transistors, at least one of said plurality of second transistors and at least one of said plurality of third transistors are aligned to each other with less than 100 nm misalignment,
wherein at least one of said plurality of second transistors is at least partially overlaying at least one of said plurality of first transistors,
wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, and
wherein at least one of said plurality of second transistors is a junction-less transistor.
9. The device according to claim 8 , further comprising:
a third memory cell comprising at least one of said plurality of third transistors;
a second memory cell comprising at least one of said plurality of second transistors; and
a memory periphery circuit comprising at least one of said plurality of first transistors,
wherein said memory periphery circuit controls said third memory cell and second memory cell.
10. The device according to claim 8 ,
wherein at least one of said plurality of second transistors is connected to at least one of said plurality of third transistors with an ohmic connection.
11. The device according to claim 8 ,
wherein said at least one through-layer via is formed through and in direct contact with a source or drain of at least one of said plurality of second transistors.
12. The device according to claim 8 ,
wherein said plurality of second transistors comprise a second gate dielectric;
wherein said plurality of third transistors comprise a third gate dielectric, and
wherein said second gate dielectric and said third gate dielectric are part of the same layer.
13. The device according to claim 8 ,
wherein at least one of said plurality of third transistors is controlled by a third control line,
wherein at least one of said plurality of second transistors is controlled by a second control line, and
wherein a control circuit controlling said second control line and third control line comprises a portion of said plurality of first transistors.
14. The device according to claim 8 ,
wherein supply of ground or power to at least one of said plurality of second transistors is controlled by at least one of said plurality of first transistors.
15. A 3D integrated circuit device, the device comprising:
a first level comprising a single crystal wafer, said first level comprises a plurality of first transistors;
a second level overlaying said first level, said second level comprises a plurality of second transistors;
a third level overlaying said second level, said third level comprises a plurality of third transistors;
a first metal layer interconnecting said plurality of first transistors;
a second metal layer overlaying said third level,
wherein said second level has a first coefficient of thermal expansion; and
a connection path connecting at least one of said second transistors to said first metal layer,
wherein said connection path comprises at least one through-layer via,
wherein said through-layer via comprises a material, said material has a second co-efficient of thermal expansion,
wherein said second co-efficient of thermal expansion is within 50 percent of said first coefficient of thermal expansion,
wherein at least one of said plurality of first transistors, at least one of said plurality of second transistors and at least one of said plurality of third transistors are aligned to each other with less than 100 nm misalignment, and
wherein at least one of said plurality of second transistors is a junction-less transistor.
16. The device according to claim 15 , further comprising:
a third memory cell comprising at least one of said plurality of third transistors;
a second memory cell comprising at least one of said plurality of second transistors; and
a memory periphery circuit comprising at least one of said plurality of first transistors,
wherein said memory periphery circuit controls said third memory cell and second memory cell.
17. The device according to claim 15 ,
wherein at least one of said plurality of second transistors is connected to at least one of said plurality of third transistors with an ohmic connection.
18. The device according to claim 15 ,
wherein said at least one through-layer via is formed through and in direct contact with a source or drain of at least one of said plurality of second transistors.
19. The device according to claim 15 ,
wherein said plurality of second transistors comprise a second gate dielectric;
wherein said plurality of third transistors comprise a third gate dielectric, and
wherein said second gate dielectric and said third gate dielectric are part of the same layer.
20. The device according to claim 15 ,
wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors.